projects / openwrt / staging / dangole.git / blob
? search:


0069c2b8e65ff7e5a0ff62d162c403123d705ae4
[openwrt/staging/dangole.git] /
1 From a961b21904be2f527afd87000d6bbf11d4ddecc8 Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.org>
3 Date: Mon, 11 Sep 2017 15:42:28 +0100
4 Subject: [PATCH 332/454] bcm2835-unicam: Driver for CCP2/CSI2 camera interface
5
6 Add driver for the Unicam camera receiver block on
7 BCM283x processors.
8
9 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
10 ---
11 drivers/media/platform/Kconfig | 1 +
12 drivers/media/platform/Makefile | 1 +
13 drivers/media/platform/bcm2835/Kconfig | 14 +
14 drivers/media/platform/bcm2835/Makefile | 3 +
15 .../media/platform/bcm2835/bcm2835-unicam.c | 2100 +++++++++++++++++
16 .../media/platform/bcm2835/vc4-regs-unicam.h | 264 +++
17 6 files changed, 2383 insertions(+)
18 create mode 100644 drivers/media/platform/bcm2835/Kconfig
19 create mode 100644 drivers/media/platform/bcm2835/Makefile
20 create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
21 create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
22
23 --- a/drivers/media/platform/Kconfig
24 +++ b/drivers/media/platform/Kconfig
25 @@ -150,6 +150,7 @@ source "drivers/media/platform/am437x/Kc
26 source "drivers/media/platform/xilinx/Kconfig"
27 source "drivers/media/platform/rcar-vin/Kconfig"
28 source "drivers/media/platform/atmel/Kconfig"
29 +source "drivers/media/platform/bcm2835/Kconfig"
30
31 config VIDEO_TI_CAL
32 tristate "TI CAL (Camera Adaptation Layer) driver"
33 --- a/drivers/media/platform/Makefile
34 +++ b/drivers/media/platform/Makefile
35 @@ -91,3 +91,4 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/
36 obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
37
38 obj-y += meson/
39 +obj-y += bcm2835/
40 --- /dev/null
41 +++ b/drivers/media/platform/bcm2835/Kconfig
42 @@ -0,0 +1,14 @@
43 +# Broadcom VideoCore4 V4L2 camera support
44 +
45 +config VIDEO_BCM2835_UNICAM
46 + tristate "Broadcom BCM2835 Unicam video capture driver"
47 + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
48 + depends on ARCH_BCM2835 || COMPILE_TEST
49 + select VIDEOBUF2_DMA_CONTIG
50 + select V4L2_FWNODE
51 + ---help---
52 + Say Y here to enable V4L2 subdevice for CSI2 receiver.
53 + This is a V4L2 subdevice that interfaces directly to the VC4 peripheral.
54 +
55 + To compile this driver as a module, choose M here. The module
56 + will be called bcm2835-unicam.
57 --- /dev/null
58 +++ b/drivers/media/platform/bcm2835/Makefile
59 @@ -0,0 +1,3 @@
60 +# Makefile for BCM2835 Unicam driver
61 +
62 +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
63 --- /dev/null
64 +++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
65 @@ -0,0 +1,2100 @@
66 +/*
67 + * BCM2835 Unicam capture Driver
68 + *
69 + * Copyright (C) 2017 - Raspberry Pi (Trading) Ltd.
70 + *
71 + * Dave Stevenson <dave.stevenson@raspberrypi.org>
72 + *
73 + * Based on TI am437x driver by Benoit Parrot and Lad, Prabhakar and
74 + * TI CAL camera interface driver by Benoit Parrot.
75 + *
76 + *
77 + * There are two camera drivers in the kernel for BCM283x - this one
78 + * and bcm2835-camera (currently in staging).
79 + *
80 + * This driver directly controls the Unicam peripheral - there is no
81 + * involvement with the VideoCore firmware. Unicam receives CSI-2 or
82 + * CCP2 data and writes it into SDRAM. The only potential processing options are
83 + * to repack Bayer data into an alternate format, and applying windowing.
84 + * The repacking does not shift the data, so could repack V4L2_PIX_FMT_Sxxxx10P
85 + * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
86 + * but not generically up to V4L2_PIX_FMT_Sxxxx16.
87 + * Adding support for repacking and windowing may be added later.
88 + *
89 + * It should be possible to connect this driver to any sensor with a
90 + * suitable output interface and V4L2 subdevice driver.
91 + *
92 + * bcm2835-camera uses the VideoCore firmware to control the sensor,
93 + * Unicam, ISP, and all tuner control loops. Fully processed frames are
94 + * delivered to the driver by the firmware. It only has sensor drivers
95 + * for Omnivision OV5647, and Sony IMX219 sensors.
96 + *
97 + * The two drivers are mutually exclusive for the same Unicam instance.
98 + * The VideoCore firmware checks the device tree configuration during boot.
99 + * If it finds device tree nodes called csi0 or csi1 it will block the
100 + * firmware from accessing the peripheral, and bcm2835-camera will
101 + * not be able to stream data.
102 + *
103 + *
104 + * This program is free software; you may redistribute it and/or modify
105 + * it under the terms of the GNU General Public License as published by
106 + * the Free Software Foundation; version 2 of the License.
107 + *
108 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
109 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
110 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
111 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
112 + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
113 + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
114 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
115 + * SOFTWARE.
116 + */
117 +
118 +#include <linux/clk.h>
119 +#include <linux/delay.h>
120 +#include <linux/device.h>
121 +#include <linux/err.h>
122 +#include <linux/init.h>
123 +#include <linux/interrupt.h>
124 +#include <linux/io.h>
125 +#include <linux/module.h>
126 +#include <linux/of_device.h>
127 +#include <linux/of_graph.h>
128 +#include <linux/pinctrl/consumer.h>
129 +#include <linux/platform_device.h>
130 +#include <linux/pm_runtime.h>
131 +#include <linux/slab.h>
132 +#include <linux/uaccess.h>
133 +#include <linux/videodev2.h>
134 +
135 +#include <media/v4l2-common.h>
136 +#include <media/v4l2-ctrls.h>
137 +#include <media/v4l2-dev.h>
138 +#include <media/v4l2-device.h>
139 +#include <media/v4l2-dv-timings.h>
140 +#include <media/v4l2-event.h>
141 +#include <media/v4l2-ioctl.h>
142 +#include <media/v4l2-fwnode.h>
143 +#include <media/videobuf2-dma-contig.h>
144 +
145 +#include "vc4-regs-unicam.h"
146 +
147 +#define UNICAM_MODULE_NAME "unicam"
148 +#define UNICAM_VERSION "0.1.0"
149 +
150 +static int debug;
151 +module_param(debug, int, 0644);
152 +MODULE_PARM_DESC(debug, "Debug level 0-3");
153 +
154 +#define unicam_dbg(level, dev, fmt, arg...) \
155 + v4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)
156 +#define unicam_info(dev, fmt, arg...) \
157 + v4l2_info(&(dev)->v4l2_dev, fmt, ##arg)
158 +#define unicam_err(dev, fmt, arg...) \
159 + v4l2_err(&(dev)->v4l2_dev, fmt, ##arg)
160 +
161 +/*
162 + * Stride is a 16 bit register, but also has to be a multiple of 16.
163 + */
164 +#define BPL_ALIGNMENT 16
165 +#define MAX_BYTESPERLINE ((1 << 16) - BPL_ALIGNMENT)
166 +/*
167 + * Max width is therefore determined by the max stride divided by
168 + * the number of bits per pixel. Take 32bpp as a
169 + * worst case.
170 + * No imposed limit on the height, so adopt a square image for want
171 + * of anything better.
172 + */
173 +#define MAX_WIDTH (MAX_BYTESPERLINE / 4)
174 +#define MAX_HEIGHT MAX_WIDTH
175 +/* Define a nominal minimum image size */
176 +#define MIN_WIDTH 16
177 +#define MIN_HEIGHT 16
178 +/*
179 + * Whilst Unicam doesn't require any additional padding on the image
180 + * height, various other parts of the BCM283x frameworks require a multiple
181 + * of 16.
182 + * Seeing as image buffers are significantly larger than this extra
183 + * padding, add it in order to simplify integration.
184 + */
185 +#define HEIGHT_ALIGNMENT 16
186 +
187 +/*
188 + * struct unicam_fmt - Unicam media bus format information
189 + * @pixelformat: V4L2 pixel format FCC identifier.
190 + * @code: V4L2 media bus format code.
191 + * @depth: Bits per pixel (when stored in memory).
192 + * @csi_dt: CSI data type.
193 + */
194 +struct unicam_fmt {
195 + u32 fourcc;
196 + u32 code;
197 + u8 depth;
198 + u8 csi_dt;
199 +};
200 +
201 +static const struct unicam_fmt formats[] = {
202 + /* YUV Formats */
203 + {
204 + .fourcc = V4L2_PIX_FMT_YUYV,
205 + .code = MEDIA_BUS_FMT_YUYV8_2X8,
206 + .depth = 16,
207 + .csi_dt = 0x1e,
208 + }, {
209 + .fourcc = V4L2_PIX_FMT_UYVY,
210 + .code = MEDIA_BUS_FMT_UYVY8_2X8,
211 + .depth = 16,
212 + .csi_dt = 0x1e,
213 + }, {
214 + .fourcc = V4L2_PIX_FMT_YVYU,
215 + .code = MEDIA_BUS_FMT_YVYU8_2X8,
216 + .depth = 16,
217 + .csi_dt = 0x1e,
218 + }, {
219 + .fourcc = V4L2_PIX_FMT_VYUY,
220 + .code = MEDIA_BUS_FMT_VYUY8_2X8,
221 + .depth = 16,
222 + .csi_dt = 0x1e,
223 + }, {
224 + .fourcc = V4L2_PIX_FMT_YUYV,
225 + .code = MEDIA_BUS_FMT_YUYV8_1X16,
226 + .depth = 16,
227 + .csi_dt = 0x1e,
228 + }, {
229 + .fourcc = V4L2_PIX_FMT_UYVY,
230 + .code = MEDIA_BUS_FMT_UYVY8_1X16,
231 + .depth = 16,
232 + .csi_dt = 0x1e,
233 + }, {
234 + .fourcc = V4L2_PIX_FMT_YVYU,
235 + .code = MEDIA_BUS_FMT_YVYU8_1X16,
236 + .depth = 16,
237 + .csi_dt = 0x1e,
238 + }, {
239 + .fourcc = V4L2_PIX_FMT_VYUY,
240 + .code = MEDIA_BUS_FMT_VYUY8_1X16,
241 + .depth = 16,
242 + .csi_dt = 0x1e,
243 + }, {
244 + /* RGB Formats */
245 + .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
246 + .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
247 + .depth = 16,
248 + .csi_dt = 0x22,
249 + }, {
250 + .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
251 + .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
252 + .depth = 16,
253 + .csi_dt = 0x22
254 + }, {
255 + .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
256 + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
257 + .depth = 16,
258 + .csi_dt = 0x21,
259 + }, {
260 + .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
261 + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
262 + .depth = 16,
263 + .csi_dt = 0x21,
264 + }, {
265 + .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
266 + .code = MEDIA_BUS_FMT_RGB888_1X24,
267 + .depth = 24,
268 + .csi_dt = 0x24,
269 + }, {
270 + .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
271 + .code = MEDIA_BUS_FMT_BGR888_1X24,
272 + .depth = 24,
273 + .csi_dt = 0x24,
274 + }, {
275 + .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
276 + .code = MEDIA_BUS_FMT_ARGB8888_1X32,
277 + .depth = 32,
278 + .csi_dt = 0x0,
279 + }, {
280 + /* Bayer Formats */
281 + .fourcc = V4L2_PIX_FMT_SBGGR8,
282 + .code = MEDIA_BUS_FMT_SBGGR8_1X8,
283 + .depth = 8,
284 + .csi_dt = 0x2a,
285 + }, {
286 + .fourcc = V4L2_PIX_FMT_SGBRG8,
287 + .code = MEDIA_BUS_FMT_SGBRG8_1X8,
288 + .depth = 8,
289 + .csi_dt = 0x2a,
290 + }, {
291 + .fourcc = V4L2_PIX_FMT_SGRBG8,
292 + .code = MEDIA_BUS_FMT_SGRBG8_1X8,
293 + .depth = 8,
294 + .csi_dt = 0x2a,
295 + }, {
296 + .fourcc = V4L2_PIX_FMT_SRGGB8,
297 + .code = MEDIA_BUS_FMT_SRGGB8_1X8,
298 + .depth = 8,
299 + .csi_dt = 0x2a,
300 + }, {
301 + .fourcc = V4L2_PIX_FMT_SBGGR10P,
302 + .code = MEDIA_BUS_FMT_SBGGR10_1X10,
303 + .depth = 10,
304 + .csi_dt = 0x2b,
305 + }, {
306 + .fourcc = V4L2_PIX_FMT_SGBRG10P,
307 + .code = MEDIA_BUS_FMT_SGBRG10_1X10,
308 + .depth = 10,
309 + .csi_dt = 0x2b,
310 + }, {
311 + .fourcc = V4L2_PIX_FMT_SGRBG10P,
312 + .code = MEDIA_BUS_FMT_SGRBG10_1X10,
313 + .depth = 10,
314 + .csi_dt = 0x2b,
315 + }, {
316 + .fourcc = V4L2_PIX_FMT_SRGGB10P,
317 + .code = MEDIA_BUS_FMT_SRGGB10_1X10,
318 + .depth = 10,
319 + .csi_dt = 0x2b,
320 + }, {
321 + .fourcc = V4L2_PIX_FMT_SBGGR12P,
322 + .code = MEDIA_BUS_FMT_SBGGR12_1X12,
323 + .depth = 12,
324 + .csi_dt = 0x2c,
325 + }, {
326 + .fourcc = V4L2_PIX_FMT_SGBRG12P,
327 + .code = MEDIA_BUS_FMT_SGBRG12_1X12,
328 + .depth = 12,
329 + .csi_dt = 0x2c,
330 + }, {
331 + .fourcc = V4L2_PIX_FMT_SGRBG12P,
332 + .code = MEDIA_BUS_FMT_SGRBG12_1X12,
333 + .depth = 12,
334 + .csi_dt = 0x2c,
335 + }, {
336 + .fourcc = V4L2_PIX_FMT_SRGGB12P,
337 + .code = MEDIA_BUS_FMT_SRGGB12_1X12,
338 + .depth = 12,
339 + .csi_dt = 0x2c,
340 + },
341 + /*
342 + * 14 and 16 bit Bayer formats could be supported, but there are no V4L2
343 + * defines for 14bit packed Bayer, and no CSI2 data_type for raw 16.
344 + */
345 +};
346 +
347 +struct unicam_dmaqueue {
348 + struct list_head active;
349 +};
350 +
351 +struct unicam_buffer {
352 + struct vb2_v4l2_buffer vb;
353 + struct list_head list;
354 +};
355 +
356 +struct unicam_cfg {
357 + /* peripheral base address */
358 + void __iomem *base;
359 + /* clock gating base address */
360 + void __iomem *clk_gate_base;
361 +};
362 +
363 +#define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))
364 +
365 +struct unicam_device {
366 + /* V4l2 specific parameters */
367 + /* Identifies video device for this channel */
368 + struct video_device video_dev;
369 + struct v4l2_ctrl_handler ctrl_handler;
370 +
371 + struct v4l2_fwnode_endpoint endpoint;
372 +
373 + struct v4l2_async_subdev asd;
374 +
375 + /* unicam cfg */
376 + struct unicam_cfg cfg;
377 + /* clock handle */
378 + struct clk *clock;
379 + /* V4l2 device */
380 + struct v4l2_device v4l2_dev;
381 + /* parent device */
382 + struct platform_device *pdev;
383 + /* subdevice async Notifier */
384 + struct v4l2_async_notifier notifier;
385 + unsigned int sequence;
386 +
387 + /* ptr to sub device */
388 + struct v4l2_subdev *sensor;
389 + /* Pad config for the sensor */
390 + struct v4l2_subdev_pad_config *sensor_config;
391 + /* current input at the sub device */
392 + int current_input;
393 +
394 + /* Pointer pointing to current v4l2_buffer */
395 + struct unicam_buffer *cur_frm;
396 + /* Pointer pointing to next v4l2_buffer */
397 + struct unicam_buffer *next_frm;
398 +
399 + /* video capture */
400 + const struct unicam_fmt *fmt;
401 + /* Used to store current pixel format */
402 + struct v4l2_format v_fmt;
403 + /* Used to store current mbus frame format */
404 + struct v4l2_mbus_framefmt m_fmt;
405 +
406 + struct unicam_fmt active_fmts[MAX_POSSIBLE_PIX_FMTS];
407 + int num_active_fmt;
408 + unsigned int virtual_channel;
409 + enum v4l2_mbus_type bus_type;
410 + /*
411 + * Stores bus.mipi_csi2.flags for CSI2 sensors, or
412 + * bus.mipi_csi1.strobe for CCP2.
413 + */
414 + unsigned int bus_flags;
415 + unsigned int max_data_lanes;
416 + unsigned int active_data_lanes;
417 +
418 + struct v4l2_rect crop;
419 +
420 + /* Currently selected input on subdev */
421 + int input;
422 +
423 + /* Buffer queue used in video-buf */
424 + struct vb2_queue buffer_queue;
425 + /* Queue of filled frames */
426 + struct unicam_dmaqueue dma_queue;
427 + /* IRQ lock for DMA queue */
428 + spinlock_t dma_queue_lock;
429 + /* lock used to access this structure */
430 + struct mutex lock;
431 + /* Flag to denote that we are processing buffers */
432 + int streaming;
433 +};
434 +
435 +/* Hardware access */
436 +#define clk_write(dev, val) writel((val) | 0x5a000000, (dev)->clk_gate_base)
437 +#define clk_read(dev) readl((dev)->clk_gate_base)
438 +
439 +#define reg_read(dev, offset) readl((dev)->base + (offset))
440 +#define reg_write(dev, offset, val) writel(val, (dev)->base + (offset))
441 +
442 +#define reg_read_field(dev, offset, mask) get_field(reg_read((dev), (offset), \
443 + mask))
444 +
445 +static inline int get_field(u32 value, u32 mask)
446 +{
447 + return (value & mask) >> __ffs(mask);
448 +}
449 +
450 +static inline void set_field(u32 *valp, u32 field, u32 mask)
451 +{
452 + u32 val = *valp;
453 +
454 + val &= ~mask;
455 + val |= (field << __ffs(mask)) & mask;
456 + *valp = val;
457 +}
458 +
459 +static inline void reg_write_field(struct unicam_cfg *dev, u32 offset,
460 + u32 field, u32 mask)
461 +{
462 + u32 val = reg_read((dev), (offset));
463 +
464 + set_field(&val, field, mask);
465 + reg_write((dev), (offset), val);
466 +}
467 +
468 +/* Power management functions */
469 +static inline int unicam_runtime_get(struct unicam_device *dev)
470 +{
471 + int r;
472 +
473 + r = pm_runtime_get_sync(&dev->pdev->dev);
474 +
475 + return r;
476 +}
477 +
478 +static inline void unicam_runtime_put(struct unicam_device *dev)
479 +{
480 + pm_runtime_put_sync(&dev->pdev->dev);
481 +}
482 +
483 +/* Format setup functions */
484 +static int find_mbus_depth_by_code(u32 code)
485 +{
486 + const struct unicam_fmt *fmt;
487 + unsigned int k;
488 +
489 + for (k = 0; k < ARRAY_SIZE(formats); k++) {
490 + fmt = &formats[k];
491 + if (fmt->code == code)
492 + return fmt->depth;
493 + }
494 +
495 + return 0;
496 +}
497 +
498 +static const struct unicam_fmt *find_format_by_code(struct unicam_device *dev,
499 + u32 code)
500 +{
501 + const struct unicam_fmt *fmt;
502 + unsigned int k;
503 +
504 + for (k = 0; k < dev->num_active_fmt; k++) {
505 + fmt = &dev->active_fmts[k];
506 + if (fmt->code == code)
507 + return fmt;
508 + }
509 +
510 + return NULL;
511 +}
512 +
513 +static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,
514 + u32 pixelformat)
515 +{
516 + const struct unicam_fmt *fmt;
517 + unsigned int k;
518 +
519 + for (k = 0; k < dev->num_active_fmt; k++) {
520 + fmt = &dev->active_fmts[k];
521 + if (fmt->fourcc == pixelformat)
522 + return fmt;
523 + }
524 +
525 + return NULL;
526 +}
527 +
528 +static void dump_active_formats(struct unicam_device *dev)
529 +{
530 + int i;
531 +
532 + for (i = 0; i < dev->num_active_fmt; i++) {
533 + unicam_dbg(3, dev, "active_fmt[%d] (%p) is code %04x, fourcc " V4L2_FOURCC_CONV ", depth %d\n",
534 + i, &dev->active_fmts[i], dev->active_fmts[i].code,
535 + V4L2_FOURCC_CONV_ARGS(dev->active_fmts[i].fourcc),
536 + dev->active_fmts[i].depth);
537 + }
538 +}
539 +
540 +static inline unsigned int bytes_per_line(u32 width,
541 + const struct unicam_fmt *fmt)
542 +{
543 + return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
544 +}
545 +
546 +static int __subdev_get_format(struct unicam_device *dev,
547 + struct v4l2_mbus_framefmt *fmt)
548 +{
549 + struct v4l2_subdev_format sd_fmt = {0};
550 + struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
551 + int ret;
552 +
553 + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
554 + sd_fmt.pad = 0;
555 +
556 + ret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,
557 + &sd_fmt);
558 + if (ret < 0)
559 + return ret;
560 +
561 + *fmt = *mbus_fmt;
562 +
563 + unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
564 + fmt->width, fmt->height, fmt->code);
565 +
566 + return 0;
567 +}
568 +
569 +static int __subdev_set_format(struct unicam_device *dev,
570 + struct v4l2_mbus_framefmt *fmt)
571 +{
572 + struct v4l2_subdev_format sd_fmt = {
573 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
574 + };
575 + struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
576 + int ret;
577 +
578 + *mbus_fmt = *fmt;
579 +
580 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
581 + &sd_fmt);
582 + if (ret < 0)
583 + return ret;
584 +
585 + unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
586 + fmt->width, fmt->height, fmt->code);
587 +
588 + return 0;
589 +}
590 +
591 +static int unicam_calc_format_size_bpl(struct unicam_device *dev,
592 + const struct unicam_fmt *fmt,
593 + struct v4l2_format *f)
594 +{
595 + unsigned int min_bytesperline;
596 +
597 + v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
598 + &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
599 + 0);
600 +
601 + min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt);
602 +
603 + if (f->fmt.pix.bytesperline > min_bytesperline &&
604 + f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
605 + f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
606 + BPL_ALIGNMENT);
607 + else
608 + f->fmt.pix.bytesperline = min_bytesperline;
609 +
610 + /* Align height up for compatibility with other hardware blocks */
611 + f->fmt.pix.sizeimage = ALIGN(f->fmt.pix.height, HEIGHT_ALIGNMENT) *
612 + f->fmt.pix.bytesperline;
613 +
614 + unicam_dbg(3, dev, "%s: fourcc: " V4L2_FOURCC_CONV " size: %dx%d bpl:%d img_size:%d\n",
615 + __func__,
616 + V4L2_FOURCC_CONV_ARGS(f->fmt.pix.pixelformat),
617 + f->fmt.pix.width, f->fmt.pix.height,
618 + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
619 +
620 + return 0;
621 +}
622 +
623 +static int unicam_reset_format(struct unicam_device *dev)
624 +{
625 + struct v4l2_mbus_framefmt mbus_fmt;
626 + int ret;
627 +
628 + ret = __subdev_get_format(dev, &mbus_fmt);
629 + if (ret) {
630 + unicam_err(dev, "Failed to get_format - ret %d\n", ret);
631 + return ret;
632 + }
633 +
634 + if (mbus_fmt.code != dev->fmt->code) {
635 + unicam_err(dev, "code mismatch - fmt->code %08x, mbus_fmt.code %08x\n",
636 + dev->fmt->code, mbus_fmt.code);
637 + return ret;
638 + }
639 +
640 + v4l2_fill_pix_format(&dev->v_fmt.fmt.pix, &mbus_fmt);
641 + dev->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
642 +
643 + unicam_calc_format_size_bpl(dev, dev->fmt, &dev->v_fmt);
644 +
645 + dev->m_fmt = mbus_fmt;
646 +
647 + return 0;
648 +}
649 +
650 +static void unicam_wr_dma_addr(struct unicam_device *dev, unsigned int dmaaddr)
651 +{
652 + unicam_dbg(1, dev, "wr_dma_addr %08x-%08x\n",
653 + dmaaddr, dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
654 + reg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);
655 + reg_write(&dev->cfg, UNICAM_IBEA0,
656 + dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
657 +}
658 +
659 +static inline void unicam_schedule_next_buffer(struct unicam_device *dev)
660 +{
661 + struct unicam_dmaqueue *dma_q = &dev->dma_queue;
662 + struct unicam_buffer *buf;
663 + dma_addr_t addr;
664 +
665 + buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
666 + dev->next_frm = buf;
667 + list_del(&buf->list);
668 +
669 + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
670 + unicam_wr_dma_addr(dev, addr);
671 +}
672 +
673 +static inline void unicam_process_buffer_complete(struct unicam_device *dev)
674 +{
675 + dev->cur_frm->vb.field = dev->m_fmt.field;
676 + dev->cur_frm->vb.sequence = dev->sequence++;
677 +
678 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
679 + dev->cur_frm = dev->next_frm;
680 +}
681 +
682 +/*
683 + * unicam_isr : ISR handler for unicam capture
684 + * @irq: irq number
685 + * @dev_id: dev_id ptr
686 + *
687 + * It changes status of the captured buffer, takes next buffer from the queue
688 + * and sets its address in unicam registers
689 + */
690 +static irqreturn_t unicam_isr(int irq, void *dev)
691 +{
692 + struct unicam_device *unicam = (struct unicam_device *)dev;
693 + struct unicam_cfg *cfg = &unicam->cfg;
694 + struct unicam_dmaqueue *dma_q = &unicam->dma_queue;
695 + int ista, sta;
696 +
697 + /*
698 + * Don't service interrupts if not streaming.
699 + * Avoids issues if the VPU should enable the
700 + * peripheral without the kernel knowing (that
701 + * shouldn't happen, but causes issues if it does).
702 + */
703 + if (!unicam->streaming)
704 + return IRQ_HANDLED;
705 +
706 + sta = reg_read(cfg, UNICAM_STA);
707 + /* Write value back to clear the interrupts */
708 + reg_write(cfg, UNICAM_STA, sta);
709 +
710 + ista = reg_read(cfg, UNICAM_ISTA);
711 + /* Write value back to clear the interrupts */
712 + reg_write(cfg, UNICAM_ISTA, ista);
713 +
714 + if (!(sta && (UNICAM_IS | UNICAM_PI0)))
715 + return IRQ_HANDLED;
716 +
717 + if (ista & UNICAM_FSI) {
718 + /*
719 + * Timestamp is to be when the first data byte was captured,
720 + * aka frame start.
721 + */
722 + if (unicam->cur_frm)
723 + unicam->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
724 + }
725 + if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
726 + /*
727 + * Ensure we have swapped buffers already as we can't
728 + * stop the peripheral. Overwrite the frame we've just
729 + * captured instead.
730 + */
731 + if (unicam->cur_frm && unicam->cur_frm != unicam->next_frm)
732 + unicam_process_buffer_complete(unicam);
733 + }
734 +
735 + if (ista & (UNICAM_FSI | UNICAM_LCI)) {
736 + spin_lock(&unicam->dma_queue_lock);
737 + if (!list_empty(&dma_q->active) &&
738 + unicam->cur_frm == unicam->next_frm)
739 + unicam_schedule_next_buffer(unicam);
740 + spin_unlock(&unicam->dma_queue_lock);
741 + }
742 +
743 + if (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {
744 + /* Switch out of trigger mode if selected */
745 + reg_write_field(&unicam->cfg, UNICAM_ICTL, 1, UNICAM_TFC);
746 + reg_write_field(&unicam->cfg, UNICAM_ICTL, 0, UNICAM_FCM);
747 + }
748 + return IRQ_HANDLED;
749 +}
750 +
751 +static int unicam_querycap(struct file *file, void *priv,
752 + struct v4l2_capability *cap)
753 +{
754 + struct unicam_device *dev = video_drvdata(file);
755 +
756 + strlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
757 + strlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
758 +
759 + snprintf(cap->bus_info, sizeof(cap->bus_info),
760 + "platform:%s", dev->v4l2_dev.name);
761 +
762 + return 0;
763 +}
764 +
765 +static int unicam_enum_fmt_vid_cap(struct file *file, void *priv,
766 + struct v4l2_fmtdesc *f)
767 +{
768 + struct unicam_device *dev = video_drvdata(file);
769 + const struct unicam_fmt *fmt = NULL;
770 +
771 + if (f->index >= dev->num_active_fmt)
772 + return -EINVAL;
773 +
774 + fmt = &dev->active_fmts[f->index];
775 +
776 + f->pixelformat = fmt->fourcc;
777 +
778 + return 0;
779 +}
780 +
781 +static int unicam_g_fmt_vid_cap(struct file *file, void *priv,
782 + struct v4l2_format *f)
783 +{
784 + struct unicam_device *dev = video_drvdata(file);
785 +
786 + *f = dev->v_fmt;
787 +
788 + return 0;
789 +}
790 +
791 +static int unicam_try_fmt_vid_cap(struct file *file, void *priv,
792 + struct v4l2_format *f)
793 +{
794 + struct unicam_device *dev = video_drvdata(file);
795 + const struct unicam_fmt *fmt;
796 + struct v4l2_subdev_format sd_fmt = {
797 + .which = V4L2_SUBDEV_FORMAT_TRY,
798 + };
799 + struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
800 + int ret;
801 +
802 + fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
803 + if (!fmt) {
804 + unicam_dbg(3, dev, "Fourcc format (0x%08x) not found. Use default of %08X\n",
805 + f->fmt.pix.pixelformat, dev->active_fmts[0].fourcc);
806 +
807 + /* Just get the first one enumerated */
808 + fmt = &dev->active_fmts[0];
809 + f->fmt.pix.pixelformat = fmt->fourcc;
810 + }
811 +
812 + v4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);
813 + /*
814 + * No support for receiving interlaced video, so never
815 + * request it from the sensor subdev.
816 + */
817 + mbus_fmt->field = V4L2_FIELD_NONE;
818 +
819 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
820 + &sd_fmt);
821 + if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
822 + return ret;
823 +
824 + if (mbus_fmt->field != V4L2_FIELD_NONE)
825 + unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
826 +
827 + v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
828 + /*
829 + * Use current colorspace for now, it will get
830 + * updated properly during s_fmt
831 + */
832 + f->fmt.pix.colorspace = dev->v_fmt.fmt.pix.colorspace;
833 + return unicam_calc_format_size_bpl(dev, fmt, f);
834 +}
835 +
836 +static int unicam_s_fmt_vid_cap(struct file *file, void *priv,
837 + struct v4l2_format *f)
838 +{
839 + struct unicam_device *dev = video_drvdata(file);
840 + struct vb2_queue *q = &dev->buffer_queue;
841 + const struct unicam_fmt *fmt;
842 + struct v4l2_mbus_framefmt mbus_fmt = {0};
843 + int ret;
844 +
845 + if (vb2_is_busy(q))
846 + return -EBUSY;
847 +
848 + ret = unicam_try_fmt_vid_cap(file, priv, f);
849 + if (ret < 0)
850 + return ret;
851 +
852 + fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
853 + if (!fmt) {
854 + /* Unknown pixel format - adopt a default */
855 + fmt = &dev->active_fmts[0];
856 + f->fmt.pix.pixelformat = fmt->fourcc;
857 + return -EINVAL;
858 + }
859 +
860 + v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
861 +
862 + ret = __subdev_set_format(dev, &mbus_fmt);
863 + if (ret) {
864 + unicam_dbg(3, dev, "%s __subdev_set_format failed %d\n",
865 + __func__, ret);
866 + return ret;
867 + }
868 +
869 + /* Just double check nothing has gone wrong */
870 + if (mbus_fmt.code != fmt->code) {
871 + unicam_dbg(3, dev,
872 + "%s subdev changed format on us, this should not happen\n",
873 + __func__);
874 + return -EINVAL;
875 + }
876 +
877 + dev->fmt = fmt;
878 + dev->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
879 + dev->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;
880 + unicam_reset_format(dev);
881 +
882 + unicam_dbg(3, dev, "%s %dx%d, mbus_fmt %08X, V4L2 pix " V4L2_FOURCC_CONV ".\n",
883 + __func__, dev->v_fmt.fmt.pix.width,
884 + dev->v_fmt.fmt.pix.height, mbus_fmt.code,
885 + V4L2_FOURCC_CONV_ARGS(dev->v_fmt.fmt.pix.pixelformat));
886 +
887 + *f = dev->v_fmt;
888 +
889 + return 0;
890 +}
891 +
892 +static int unicam_queue_setup(struct vb2_queue *vq,
893 + unsigned int *nbuffers,
894 + unsigned int *nplanes,
895 + unsigned int sizes[],
896 + struct device *alloc_devs[])
897 +{
898 + struct unicam_device *dev = vb2_get_drv_priv(vq);
899 + unsigned int size = dev->v_fmt.fmt.pix.sizeimage;
900 +
901 + if (vq->num_buffers + *nbuffers < 3)
902 + *nbuffers = 3 - vq->num_buffers;
903 +
904 + if (*nplanes) {
905 + if (sizes[0] < size) {
906 + unicam_err(dev, "sizes[0] %i < size %u\n", sizes[0],
907 + size);
908 + return -EINVAL;
909 + }
910 + size = sizes[0];
911 + }
912 +
913 + *nplanes = 1;
914 + sizes[0] = size;
915 +
916 + return 0;
917 +}
918 +
919 +static int unicam_buffer_prepare(struct vb2_buffer *vb)
920 +{
921 + struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
922 + struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
923 + vb.vb2_buf);
924 + unsigned long size;
925 +
926 + if (WARN_ON(!dev->fmt))
927 + return -EINVAL;
928 +
929 + size = dev->v_fmt.fmt.pix.sizeimage;
930 + if (vb2_plane_size(vb, 0) < size) {
931 + unicam_err(dev, "data will not fit into plane (%lu < %lu)\n",
932 + vb2_plane_size(vb, 0), size);
933 + return -EINVAL;
934 + }
935 +
936 + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
937 + return 0;
938 +}
939 +
940 +static void unicam_buffer_queue(struct vb2_buffer *vb)
941 +{
942 + struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
943 + struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
944 + vb.vb2_buf);
945 + struct unicam_dmaqueue *dma_queue = &dev->dma_queue;
946 + unsigned long flags = 0;
947 +
948 + /* recheck locking */
949 + spin_lock_irqsave(&dev->dma_queue_lock, flags);
950 + list_add_tail(&buf->list, &dma_queue->active);
951 + spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
952 +}
953 +
954 +static void unicam_wr_dma_config(struct unicam_device *dev,
955 + unsigned int stride)
956 +{
957 + reg_write(&dev->cfg, UNICAM_IBLS, stride);
958 +}
959 +
960 +static void unicam_set_packing_config(struct unicam_device *dev)
961 +{
962 + int mbus_depth = find_mbus_depth_by_code(dev->fmt->code);
963 + int v4l2_depth = dev->fmt->depth;
964 + int pack, unpack;
965 + u32 val;
966 +
967 + if (mbus_depth == v4l2_depth) {
968 + unpack = UNICAM_PUM_NONE;
969 + pack = UNICAM_PPM_NONE;
970 + } else {
971 + switch (mbus_depth) {
972 + case 8:
973 + unpack = UNICAM_PUM_UNPACK8;
974 + break;
975 + case 10:
976 + unpack = UNICAM_PUM_UNPACK10;
977 + break;
978 + case 12:
979 + unpack = UNICAM_PUM_UNPACK12;
980 + break;
981 + case 14:
982 + unpack = UNICAM_PUM_UNPACK14;
983 + break;
984 + case 16:
985 + unpack = UNICAM_PUM_UNPACK16;
986 + break;
987 + default:
988 + unpack = UNICAM_PUM_NONE;
989 + break;
990 + }
991 + switch (v4l2_depth) {
992 + case 8:
993 + pack = UNICAM_PPM_PACK8;
994 + break;
995 + case 10:
996 + pack = UNICAM_PPM_PACK10;
997 + break;
998 + case 12:
999 + pack = UNICAM_PPM_PACK12;
1000 + break;
1001 + case 14:
1002 + pack = UNICAM_PPM_PACK14;
1003 + break;
1004 + case 16:
1005 + pack = UNICAM_PPM_PACK16;
1006 + break;
1007 + default:
1008 + pack = UNICAM_PPM_NONE;
1009 + break;
1010 + }
1011 + }
1012 +
1013 + val = 0;
1014 + set_field(&val, 2, UNICAM_DEBL_MASK);
1015 + set_field(&val, unpack, UNICAM_PUM_MASK);
1016 + set_field(&val, pack, UNICAM_PPM_MASK);
1017 + reg_write(&dev->cfg, UNICAM_IPIPE, val);
1018 +}
1019 +
1020 +static void unicam_cfg_image_id(struct unicam_device *dev)
1021 +{
1022 + struct unicam_cfg *cfg = &dev->cfg;
1023 +
1024 + if (dev->bus_type == V4L2_MBUS_CSI2) {
1025 + /* CSI2 mode */
1026 + reg_write(cfg, UNICAM_IDI0,
1027 + (dev->virtual_channel << 6) | dev->fmt->csi_dt);
1028 + } else {
1029 + /* CCP2 mode */
1030 + reg_write(cfg, UNICAM_IDI0, (0x80 | dev->fmt->csi_dt));
1031 + }
1032 +}
1033 +
1034 +void unicam_start_rx(struct unicam_device *dev, unsigned long addr)
1035 +{
1036 + struct unicam_cfg *cfg = &dev->cfg;
1037 + int line_int_freq = dev->v_fmt.fmt.pix.height >> 2;
1038 + unsigned int i;
1039 + u32 val;
1040 +
1041 + if (line_int_freq < 128)
1042 + line_int_freq = 128;
1043 +
1044 + /* Enable lane clocks */
1045 + val = 1;
1046 + for (i = 0; i < dev->active_data_lanes; i++)
1047 + val = val << 2 | 1;
1048 + clk_write(cfg, val);
1049 +
1050 + /* Basic init */
1051 + reg_write(cfg, UNICAM_CTRL, UNICAM_MEM);
1052 +
1053 + /* Enable analogue control, and leave in reset. */
1054 + val = UNICAM_AR;
1055 + set_field(&val, 7, UNICAM_CTATADJ_MASK);
1056 + set_field(&val, 7, UNICAM_PTATADJ_MASK);
1057 + reg_write(cfg, UNICAM_ANA, val);
1058 + usleep_range(1000, 2000);
1059 +
1060 + /* Come out of reset */
1061 + reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_AR);
1062 +
1063 + /* Peripheral reset */
1064 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
1065 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
1066 +
1067 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
1068 +
1069 + /* Enable Rx control. */
1070 + val = reg_read(cfg, UNICAM_CTRL);
1071 + if (dev->bus_type == V4L2_MBUS_CSI2) {
1072 + set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
1073 + set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
1074 + } else {
1075 + set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
1076 + set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
1077 + }
1078 + /* Packet framer timeout */
1079 + set_field(&val, 0xf, UNICAM_PFT_MASK);
1080 + set_field(&val, 128, UNICAM_OET_MASK);
1081 + reg_write(cfg, UNICAM_CTRL, val);
1082 +
1083 + reg_write(cfg, UNICAM_IHWIN, 0);
1084 + reg_write(cfg, UNICAM_IVWIN, 0);
1085 +
1086 + /* AXI bus access QoS setup */
1087 + val = reg_read(&dev->cfg, UNICAM_PRI);
1088 + set_field(&val, 0, UNICAM_BL_MASK);
1089 + set_field(&val, 0, UNICAM_BS_MASK);
1090 + set_field(&val, 0xe, UNICAM_PP_MASK);
1091 + set_field(&val, 8, UNICAM_NP_MASK);
1092 + set_field(&val, 2, UNICAM_PT_MASK);
1093 + set_field(&val, 1, UNICAM_PE);
1094 + reg_write(cfg, UNICAM_PRI, val);
1095 +
1096 + reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);
1097 +
1098 + /* Always start in trigger frame capture mode (UNICAM_FCM set) */
1099 + val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;
1100 + set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
1101 + reg_write(cfg, UNICAM_ICTL, val);
1102 + reg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);
1103 + reg_write(cfg, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
1104 +
1105 + /* tclk_term_en */
1106 + reg_write_field(cfg, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
1107 + /* tclk_settle */
1108 + reg_write_field(cfg, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
1109 + /* td_term_en */
1110 + reg_write_field(cfg, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
1111 + /* ths_settle */
1112 + reg_write_field(cfg, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
1113 + /* trx_enable */
1114 + reg_write_field(cfg, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
1115 +
1116 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_SOE);
1117 +
1118 + /* Packet compare setup - required to avoid missing frame ends */
1119 + val = 0;
1120 + set_field(&val, 1, UNICAM_PCE);
1121 + set_field(&val, 1, UNICAM_GI);
1122 + set_field(&val, 1, UNICAM_CPH);
1123 + set_field(&val, 0, UNICAM_PCVC_MASK);
1124 + set_field(&val, 1, UNICAM_PCDT_MASK);
1125 + reg_write(cfg, UNICAM_CMP0, val);
1126 +
1127 + /* Enable clock lane and set up terminations */
1128 + val = 0;
1129 + if (dev->bus_type == V4L2_MBUS_CSI2) {
1130 + /* CSI2 */
1131 + set_field(&val, 1, UNICAM_CLE);
1132 + set_field(&val, 1, UNICAM_CLLPE);
1133 + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1134 + set_field(&val, 1, UNICAM_CLTRE);
1135 + set_field(&val, 1, UNICAM_CLHSE);
1136 + }
1137 + } else {
1138 + /* CCP2 */
1139 + set_field(&val, 1, UNICAM_CLE);
1140 + set_field(&val, 1, UNICAM_CLHSE);
1141 + set_field(&val, 1, UNICAM_CLTRE);
1142 + }
1143 + reg_write(cfg, UNICAM_CLK, val);
1144 +
1145 + /*
1146 + * Enable required data lanes with appropriate terminations.
1147 + * The same value needs to be written to UNICAM_DATn registers for
1148 + * the active lanes, and 0 for inactive ones.
1149 + */
1150 + val = 0;
1151 + if (dev->bus_type == V4L2_MBUS_CSI2) {
1152 + /* CSI2 */
1153 + set_field(&val, 1, UNICAM_DLE);
1154 + set_field(&val, 1, UNICAM_DLLPE);
1155 + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1156 + set_field(&val, 1, UNICAM_DLTRE);
1157 + set_field(&val, 1, UNICAM_DLHSE);
1158 + }
1159 + } else {
1160 + /* CCP2 */
1161 + set_field(&val, 1, UNICAM_DLE);
1162 + set_field(&val, 1, UNICAM_DLHSE);
1163 + set_field(&val, 1, UNICAM_DLTRE);
1164 + }
1165 + reg_write(cfg, UNICAM_DAT0, val);
1166 +
1167 + if (dev->active_data_lanes == 1)
1168 + val = 0;
1169 + reg_write(cfg, UNICAM_DAT1, val);
1170 +
1171 + if (dev->max_data_lanes > 2) {
1172 + /*
1173 + * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
1174 + * instance supports more than 2 data lanes.
1175 + */
1176 + if (dev->active_data_lanes == 2)
1177 + val = 0;
1178 + reg_write(cfg, UNICAM_DAT2, val);
1179 +
1180 + if (dev->active_data_lanes == 3)
1181 + val = 0;
1182 + reg_write(cfg, UNICAM_DAT3, val);
1183 + }
1184 +
1185 + unicam_wr_dma_config(dev, dev->v_fmt.fmt.pix.bytesperline);
1186 + unicam_wr_dma_addr(dev, addr);
1187 + unicam_set_packing_config(dev);
1188 + unicam_cfg_image_id(dev);
1189 +
1190 + /* Disabled embedded data */
1191 + val = 0;
1192 + set_field(&val, 0, UNICAM_EDL_MASK);
1193 + reg_write(cfg, UNICAM_DCS, val);
1194 +
1195 + val = reg_read(cfg, UNICAM_MISC);
1196 + set_field(&val, 1, UNICAM_FL0);
1197 + set_field(&val, 1, UNICAM_FL1);
1198 + reg_write(cfg, UNICAM_MISC, val);
1199 +
1200 + /* Enable peripheral */
1201 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);
1202 +
1203 + /* Load image pointers */
1204 + reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
1205 +
1206 + /*
1207 + * Enable trigger only for the first frame to
1208 + * sync correctly to the FS from the source.
1209 + */
1210 + reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_TFC);
1211 +}
1212 +
1213 +static void unicam_disable(struct unicam_device *dev)
1214 +{
1215 + struct unicam_cfg *cfg = &dev->cfg;
1216 +
1217 + /* Analogue lane control disable */
1218 + reg_write_field(cfg, UNICAM_ANA, 1, UNICAM_DDL);
1219 +
1220 + /* Stop the output engine */
1221 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_SOE);
1222 +
1223 + /* Disable the data lanes. */
1224 + reg_write(cfg, UNICAM_DAT0, 0);
1225 + reg_write(cfg, UNICAM_DAT1, 0);
1226 +
1227 + if (dev->max_data_lanes > 2) {
1228 + reg_write(cfg, UNICAM_DAT2, 0);
1229 + reg_write(cfg, UNICAM_DAT3, 0);
1230 + }
1231 +
1232 + /* Peripheral reset */
1233 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
1234 + usleep_range(50, 100);
1235 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
1236 +
1237 + /* Disable peripheral */
1238 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
1239 +
1240 + /* Disable all lane clocks */
1241 + clk_write(cfg, 0);
1242 +}
1243 +
1244 +static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
1245 +{
1246 + struct unicam_device *dev = vb2_get_drv_priv(vq);
1247 + struct unicam_dmaqueue *dma_q = &dev->dma_queue;
1248 + struct unicam_buffer *buf, *tmp;
1249 + unsigned long addr = 0;
1250 + unsigned long flags;
1251 + int ret;
1252 +
1253 + spin_lock_irqsave(&dev->dma_queue_lock, flags);
1254 + buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
1255 + dev->cur_frm = buf;
1256 + dev->next_frm = buf;
1257 + list_del(&buf->list);
1258 + spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1259 +
1260 + addr = vb2_dma_contig_plane_dma_addr(&dev->cur_frm->vb.vb2_buf, 0);
1261 + dev->sequence = 0;
1262 +
1263 + ret = unicam_runtime_get(dev);
1264 + if (ret < 0) {
1265 + unicam_dbg(3, dev, "unicam_runtime_get failed\n");
1266 + goto err_release_buffers;
1267 + }
1268 +
1269 + dev->active_data_lanes = dev->max_data_lanes;
1270 + if (dev->bus_type == V4L2_MBUS_CSI2 &&
1271 + v4l2_subdev_has_op(dev->sensor, video, g_mbus_config)) {
1272 + struct v4l2_mbus_config mbus_config;
1273 +
1274 + ret = v4l2_subdev_call(dev->sensor, video, g_mbus_config,
1275 + &mbus_config);
1276 + if (ret < 0) {
1277 + unicam_dbg(3, dev, "g_mbus_config failed\n");
1278 + goto err_pm_put;
1279 + }
1280 +
1281 + dev->active_data_lanes =
1282 + (mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>
1283 + __ffs(V4L2_MBUS_CSI2_LANE_MASK);
1284 + if (!dev->active_data_lanes)
1285 + dev->active_data_lanes = dev->max_data_lanes;
1286 + }
1287 + if (dev->active_data_lanes > dev->max_data_lanes) {
1288 + unicam_err(dev, "Device has requested %u data lanes, which is >%u configured in DT\n",
1289 + dev->active_data_lanes, dev->max_data_lanes);
1290 + ret = -EINVAL;
1291 + goto err_pm_put;
1292 + }
1293 +
1294 + unicam_dbg(1, dev, "Running with %u data lanes\n",
1295 + dev->active_data_lanes);
1296 +
1297 + ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
1298 + if (ret) {
1299 + unicam_err(dev, "failed to set up clock\n");
1300 + goto err_pm_put;
1301 + }
1302 +
1303 + ret = clk_prepare_enable(dev->clock);
1304 + if (ret) {
1305 + unicam_err(dev, "Failed to enable CSI clock: %d\n", ret);
1306 + goto err_pm_put;
1307 + }
1308 + ret = v4l2_subdev_call(dev->sensor, core, s_power, 1);
1309 + if (ret < 0 && ret != -ENOIOCTLCMD) {
1310 + unicam_err(dev, "power on failed in subdev\n");
1311 + goto err_clock_unprepare;
1312 + }
1313 + dev->streaming = 1;
1314 +
1315 + unicam_start_rx(dev, addr);
1316 +
1317 + ret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);
1318 + if (ret < 0) {
1319 + unicam_err(dev, "stream on failed in subdev\n");
1320 + goto err_disable_unicam;
1321 + }
1322 +
1323 + return 0;
1324 +
1325 +err_disable_unicam:
1326 + unicam_disable(dev);
1327 + v4l2_subdev_call(dev->sensor, core, s_power, 0);
1328 +err_clock_unprepare:
1329 + clk_disable_unprepare(dev->clock);
1330 +err_pm_put:
1331 + unicam_runtime_put(dev);
1332 +err_release_buffers:
1333 + list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1334 + list_del(&buf->list);
1335 + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1336 + }
1337 + if (dev->cur_frm != dev->next_frm)
1338 + vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
1339 + VB2_BUF_STATE_QUEUED);
1340 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1341 + dev->next_frm = NULL;
1342 + dev->cur_frm = NULL;
1343 +
1344 + return ret;
1345 +}
1346 +
1347 +static void unicam_stop_streaming(struct vb2_queue *vq)
1348 +{
1349 + struct unicam_device *dev = vb2_get_drv_priv(vq);
1350 + struct unicam_dmaqueue *dma_q = &dev->dma_queue;
1351 + struct unicam_buffer *buf, *tmp;
1352 + unsigned long flags;
1353 +
1354 + if (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)
1355 + unicam_err(dev, "stream off failed in subdev\n");
1356 +
1357 + unicam_disable(dev);
1358 +
1359 + /* Release all active buffers */
1360 + spin_lock_irqsave(&dev->dma_queue_lock, flags);
1361 + list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1362 + list_del(&buf->list);
1363 + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1364 + }
1365 +
1366 + if (dev->cur_frm == dev->next_frm) {
1367 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1368 + } else {
1369 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1370 + vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
1371 + VB2_BUF_STATE_ERROR);
1372 + }
1373 + dev->cur_frm = NULL;
1374 + dev->next_frm = NULL;
1375 + spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1376 +
1377 + if (v4l2_subdev_has_op(dev->sensor, core, s_power)) {
1378 + if (v4l2_subdev_call(dev->sensor, core, s_power, 0) < 0)
1379 + unicam_err(dev, "power off failed in subdev\n");
1380 + }
1381 +
1382 + clk_disable_unprepare(dev->clock);
1383 + unicam_runtime_put(dev);
1384 +}
1385 +
1386 +static int unicam_enum_input(struct file *file, void *priv,
1387 + struct v4l2_input *inp)
1388 +{
1389 + struct unicam_device *dev = video_drvdata(file);
1390 +
1391 + if (inp->index != 0)
1392 + return -EINVAL;
1393 +
1394 + inp->type = V4L2_INPUT_TYPE_CAMERA;
1395 + if (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {
1396 + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1397 + inp->std = 0;
1398 + } else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {
1399 + inp->capabilities = V4L2_IN_CAP_STD;
1400 + if (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)
1401 + < 0)
1402 + inp->std = V4L2_STD_ALL;
1403 + } else {
1404 + inp->capabilities = 0;
1405 + inp->std = 0;
1406 + }
1407 + sprintf(inp->name, "Camera 0");
1408 + return 0;
1409 +}
1410 +
1411 +static int unicam_g_input(struct file *file, void *priv, unsigned int *i)
1412 +{
1413 + *i = 0;
1414 +
1415 + return 0;
1416 +}
1417 +
1418 +static int unicam_s_input(struct file *file, void *priv, unsigned int i)
1419 +{
1420 + /*
1421 + * FIXME: Ideally we would like to be able to query the source
1422 + * subdevice for information over the input connectors it supports,
1423 + * and map that through in to a call to video_ops->s_routing.
1424 + * There is no infrastructure support for defining that within
1425 + * devicetree at present. Until that is implemented we can't
1426 + * map a user physical connector number to s_routing input number.
1427 + */
1428 + if (i > 0)
1429 + return -EINVAL;
1430 +
1431 + return 0;
1432 +}
1433 +
1434 +static int unicam_querystd(struct file *file, void *priv,
1435 + v4l2_std_id *std)
1436 +{
1437 + struct unicam_device *dev = video_drvdata(file);
1438 +
1439 + return v4l2_subdev_call(dev->sensor, video, querystd, std);
1440 +}
1441 +
1442 +static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)
1443 +{
1444 + struct unicam_device *dev = video_drvdata(file);
1445 +
1446 + return v4l2_subdev_call(dev->sensor, video, g_std, std);
1447 +}
1448 +
1449 +static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)
1450 +{
1451 + struct unicam_device *dev = video_drvdata(file);
1452 + int ret;
1453 + v4l2_std_id current_std;
1454 +
1455 + ret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);
1456 + if (ret)
1457 + return ret;
1458 +
1459 + if (std == current_std)
1460 + return 0;
1461 +
1462 + if (vb2_is_busy(&dev->buffer_queue))
1463 + return -EBUSY;
1464 +
1465 + ret = v4l2_subdev_call(dev->sensor, video, s_std, std);
1466 +
1467 + /* Force recomputation of bytesperline */
1468 + dev->v_fmt.fmt.pix.bytesperline = 0;
1469 +
1470 + unicam_reset_format(dev);
1471 +
1472 + return ret;
1473 +}
1474 +
1475 +static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1476 +{
1477 + struct unicam_device *dev = video_drvdata(file);
1478 +
1479 + return v4l2_subdev_call(dev->sensor, pad, set_edid, edid);
1480 +}
1481 +
1482 +static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1483 +{
1484 + struct unicam_device *dev = video_drvdata(file);
1485 +
1486 + return v4l2_subdev_call(dev->sensor, pad, get_edid, edid);
1487 +}
1488 +
1489 +static int unicam_g_dv_timings(struct file *file, void *priv,
1490 + struct v4l2_dv_timings *timings)
1491 +{
1492 + struct unicam_device *dev = video_drvdata(file);
1493 +
1494 + return v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);
1495 +}
1496 +
1497 +static int unicam_s_dv_timings(struct file *file, void *priv,
1498 + struct v4l2_dv_timings *timings)
1499 +{
1500 + struct unicam_device *dev = video_drvdata(file);
1501 + struct v4l2_dv_timings current_timings;
1502 + int ret;
1503 +
1504 + ret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,
1505 + &current_timings);
1506 +
1507 + if (v4l2_match_dv_timings(timings, &current_timings, 0, false))
1508 + return 0;
1509 +
1510 + if (vb2_is_busy(&dev->buffer_queue))
1511 + return -EBUSY;
1512 +
1513 + ret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);
1514 +
1515 + /* Force recomputation of bytesperline */
1516 + dev->v_fmt.fmt.pix.bytesperline = 0;
1517 +
1518 + unicam_reset_format(dev);
1519 +
1520 + return ret;
1521 +}
1522 +
1523 +static int unicam_query_dv_timings(struct file *file, void *priv,
1524 + struct v4l2_dv_timings *timings)
1525 +{
1526 + struct unicam_device *dev = video_drvdata(file);
1527 +
1528 + return v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);
1529 +}
1530 +
1531 +static int unicam_enum_dv_timings(struct file *file, void *priv,
1532 + struct v4l2_enum_dv_timings *timings)
1533 +{
1534 + struct unicam_device *dev = video_drvdata(file);
1535 +
1536 + return v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);
1537 +}
1538 +
1539 +static int unicam_dv_timings_cap(struct file *file, void *priv,
1540 + struct v4l2_dv_timings_cap *cap)
1541 +{
1542 + struct unicam_device *dev = video_drvdata(file);
1543 +
1544 + return v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);
1545 +}
1546 +
1547 +static int unicam_subscribe_event(struct v4l2_fh *fh,
1548 + const struct v4l2_event_subscription *sub)
1549 +{
1550 + switch (sub->type) {
1551 + case V4L2_EVENT_SOURCE_CHANGE:
1552 + return v4l2_event_subscribe(fh, sub, 4, NULL);
1553 + }
1554 +
1555 + return v4l2_ctrl_subscribe_event(fh, sub);
1556 +}
1557 +
1558 +static int unicam_log_status(struct file *file, void *fh)
1559 +{
1560 + struct unicam_device *dev = video_drvdata(file);
1561 + struct unicam_cfg *cfg = &dev->cfg;
1562 + u32 reg;
1563 +
1564 + /* status for sub devices */
1565 + v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
1566 +
1567 + unicam_info(dev, "-----Receiver status-----\n");
1568 + unicam_info(dev, "V4L2 width/height: %ux%u\n",
1569 + dev->v_fmt.fmt.pix.width, dev->v_fmt.fmt.pix.height);
1570 + unicam_info(dev, "Mediabus format: %08x\n", dev->fmt->code);
1571 + unicam_info(dev, "V4L2 format: " V4L2_FOURCC_CONV "\n",
1572 + V4L2_FOURCC_CONV_ARGS(dev->v_fmt.fmt.pix.pixelformat));
1573 + reg = reg_read(&dev->cfg, UNICAM_IPIPE);
1574 + unicam_info(dev, "Unpacking/packing: %u / %u\n",
1575 + get_field(reg, UNICAM_PUM_MASK),
1576 + get_field(reg, UNICAM_PPM_MASK));
1577 + unicam_info(dev, "----Live data----\n");
1578 + unicam_info(dev, "Programmed stride: %4u\n",
1579 + reg_read(cfg, UNICAM_IBLS));
1580 + unicam_info(dev, "Detected resolution: %ux%u\n",
1581 + reg_read(cfg, UNICAM_IHSTA),
1582 + reg_read(cfg, UNICAM_IVSTA));
1583 + unicam_info(dev, "Write pointer: %08x\n",
1584 + reg_read(cfg, UNICAM_IBWP));
1585 +
1586 + return 0;
1587 +}
1588 +
1589 +static void unicam_notify(struct v4l2_subdev *sd,
1590 + unsigned int notification, void *arg)
1591 +{
1592 + struct unicam_device *dev =
1593 + container_of(sd->v4l2_dev, struct unicam_device, v4l2_dev);
1594 +
1595 + switch (notification) {
1596 + case V4L2_DEVICE_NOTIFY_EVENT:
1597 + v4l2_event_queue(&dev->video_dev, arg);
1598 + break;
1599 + default:
1600 + break;
1601 + }
1602 +}
1603 +
1604 +static const struct vb2_ops unicam_video_qops = {
1605 + .wait_prepare = vb2_ops_wait_prepare,
1606 + .wait_finish = vb2_ops_wait_finish,
1607 + .queue_setup = unicam_queue_setup,
1608 + .buf_prepare = unicam_buffer_prepare,
1609 + .buf_queue = unicam_buffer_queue,
1610 + .start_streaming = unicam_start_streaming,
1611 + .stop_streaming = unicam_stop_streaming,
1612 +};
1613 +
1614 +/* unicam capture driver file operations */
1615 +static const struct v4l2_file_operations unicam_fops = {
1616 + .owner = THIS_MODULE,
1617 + .open = v4l2_fh_open,
1618 + .release = vb2_fop_release,
1619 + .read = vb2_fop_read,
1620 + .poll = vb2_fop_poll,
1621 + .unlocked_ioctl = video_ioctl2,
1622 + .mmap = vb2_fop_mmap,
1623 +};
1624 +
1625 +/* unicam capture ioctl operations */
1626 +static const struct v4l2_ioctl_ops unicam_ioctl_ops = {
1627 + .vidioc_querycap = unicam_querycap,
1628 + .vidioc_enum_fmt_vid_cap = unicam_enum_fmt_vid_cap,
1629 + .vidioc_g_fmt_vid_cap = unicam_g_fmt_vid_cap,
1630 + .vidioc_s_fmt_vid_cap = unicam_s_fmt_vid_cap,
1631 + .vidioc_try_fmt_vid_cap = unicam_try_fmt_vid_cap,
1632 +
1633 + .vidioc_enum_input = unicam_enum_input,
1634 + .vidioc_g_input = unicam_g_input,
1635 + .vidioc_s_input = unicam_s_input,
1636 +
1637 + .vidioc_querystd = unicam_querystd,
1638 + .vidioc_s_std = unicam_s_std,
1639 + .vidioc_g_std = unicam_g_std,
1640 +
1641 + .vidioc_g_edid = unicam_g_edid,
1642 + .vidioc_s_edid = unicam_s_edid,
1643 +
1644 + .vidioc_s_dv_timings = unicam_s_dv_timings,
1645 + .vidioc_g_dv_timings = unicam_g_dv_timings,
1646 + .vidioc_query_dv_timings = unicam_query_dv_timings,
1647 + .vidioc_enum_dv_timings = unicam_enum_dv_timings,
1648 + .vidioc_dv_timings_cap = unicam_dv_timings_cap,
1649 +
1650 + .vidioc_reqbufs = vb2_ioctl_reqbufs,
1651 + .vidioc_create_bufs = vb2_ioctl_create_bufs,
1652 + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1653 + .vidioc_querybuf = vb2_ioctl_querybuf,
1654 + .vidioc_qbuf = vb2_ioctl_qbuf,
1655 + .vidioc_dqbuf = vb2_ioctl_dqbuf,
1656 + .vidioc_expbuf = vb2_ioctl_expbuf,
1657 + .vidioc_streamon = vb2_ioctl_streamon,
1658 + .vidioc_streamoff = vb2_ioctl_streamoff,
1659 +
1660 + .vidioc_log_status = unicam_log_status,
1661 + .vidioc_subscribe_event = unicam_subscribe_event,
1662 + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1663 +};
1664 +
1665 +/*
1666 + * Adds an entry to the active_fmts array
1667 + * Returns non-zero if attempting to write off the end of the array.
1668 + */
1669 +static int unicam_add_active_format(struct unicam_device *unicam,
1670 + const struct unicam_fmt *fmt)
1671 +{
1672 + //Ensure we don't run off the end of the array.
1673 + if (unicam->num_active_fmt >= MAX_POSSIBLE_PIX_FMTS)
1674 + return 1;
1675 +
1676 + unicam->active_fmts[unicam->num_active_fmt] = *fmt;
1677 + unicam_dbg(2, unicam,
1678 + "matched fourcc: " V4L2_FOURCC_CONV ": code: %04x idx: %d\n",
1679 + V4L2_FOURCC_CONV_ARGS(fmt->fourcc),
1680 + fmt->code, unicam->num_active_fmt);
1681 + unicam->num_active_fmt++;
1682 +
1683 + return 0;
1684 +}
1685 +
1686 +static int
1687 +unicam_async_bound(struct v4l2_async_notifier *notifier,
1688 + struct v4l2_subdev *subdev,
1689 + struct v4l2_async_subdev *asd)
1690 +{
1691 + struct unicam_device *unicam = container_of(notifier->v4l2_dev,
1692 + struct unicam_device, v4l2_dev);
1693 + struct v4l2_subdev_mbus_code_enum mbus_code;
1694 + int ret = 0;
1695 + int j;
1696 +
1697 + if (unicam->sensor) {
1698 + unicam_info(unicam, "Rejecting subdev %s (Already set!!)",
1699 + subdev->name);
1700 + return 0;
1701 + }
1702 +
1703 + unicam->sensor = subdev;
1704 + unicam_dbg(1, unicam, "Using sensor %s for capture\n", subdev->name);
1705 +
1706 + /* Enumerate sub device formats and enable all matching local formats */
1707 + unicam->num_active_fmt = 0;
1708 + unicam_dbg(2, unicam, "Get supported formats...\n");
1709 + for (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {
1710 + const struct unicam_fmt *fmt = NULL;
1711 + int k;
1712 +
1713 + memset(&mbus_code, 0, sizeof(mbus_code));
1714 + mbus_code.index = j;
1715 + ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
1716 + NULL, &mbus_code);
1717 + if (ret < 0) {
1718 + unicam_dbg(2, unicam,
1719 + "subdev->enum_mbus_code idx %d returned %d - continue\n",
1720 + j, ret);
1721 + continue;
1722 + }
1723 +
1724 + unicam_dbg(2, unicam, "subdev %s: code: %04x idx: %d\n",
1725 + subdev->name, mbus_code.code, j);
1726 +
1727 + for (k = 0; k < ARRAY_SIZE(formats); k++) {
1728 + if (mbus_code.code == formats[k].code) {
1729 + fmt = &formats[k];
1730 + break;
1731 + }
1732 + }
1733 + unicam_dbg(2, unicam, "fmt %04x returned as %p, V4L2 FOURCC %04x, csi_dt %02X\n",
1734 + mbus_code.code, fmt, fmt ? fmt->fourcc : 0,
1735 + fmt ? fmt->csi_dt : 0);
1736 + if (fmt) {
1737 + if (unicam_add_active_format(unicam, fmt)) {
1738 + unicam_dbg(1, unicam, "Active fmt list truncated\n");
1739 + break;
1740 + }
1741 + }
1742 + }
1743 + unicam_dbg(2, unicam,
1744 + "Done all formats\n");
1745 + dump_active_formats(unicam);
1746 +
1747 + return 0;
1748 +}
1749 +
1750 +static int unicam_probe_complete(struct unicam_device *unicam)
1751 +{
1752 + struct video_device *vdev;
1753 + struct vb2_queue *q;
1754 + struct v4l2_mbus_framefmt mbus_fmt = {0};
1755 + const struct unicam_fmt *fmt;
1756 + int ret;
1757 +
1758 + v4l2_set_subdev_hostdata(unicam->sensor, unicam);
1759 +
1760 + unicam->v4l2_dev.notify = unicam_notify;
1761 +
1762 + unicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);
1763 + if (!unicam->sensor_config)
1764 + return -ENOMEM;
1765 +
1766 + ret = __subdev_get_format(unicam, &mbus_fmt);
1767 + if (ret) {
1768 + unicam_err(unicam, "Failed to get_format - ret %d\n", ret);
1769 + return ret;
1770 + }
1771 +
1772 + fmt = find_format_by_code(unicam, mbus_fmt.code);
1773 + if (!fmt) {
1774 + /* Default image format not valid. Choose first active fmt. */
1775 + fmt = &unicam->active_fmts[0];
1776 + mbus_fmt.code = fmt->code;
1777 + ret = __subdev_set_format(unicam, &mbus_fmt);
1778 + if (ret)
1779 + return -EINVAL;
1780 + }
1781 + if (mbus_fmt.field != V4L2_FIELD_NONE) {
1782 + /* Interlaced not supported - disable it now. */
1783 + mbus_fmt.field = V4L2_FIELD_NONE;
1784 + ret = __subdev_set_format(unicam, &mbus_fmt);
1785 + if (ret)
1786 + return -EINVAL;
1787 + }
1788 +
1789 + unicam->fmt = fmt;
1790 + unicam->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1791 +
1792 + /* Read current subdev format */
1793 + unicam_reset_format(unicam);
1794 +
1795 + if (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
1796 + v4l2_std_id tvnorms;
1797 +
1798 + if (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,
1799 + g_tvnorms)))
1800 + /*
1801 + * Subdevice should not advertise s_std but not
1802 + * g_tvnorms
1803 + */
1804 + return -EINVAL;
1805 +
1806 + ret = v4l2_subdev_call(unicam->sensor, video,
1807 + g_tvnorms, &tvnorms);
1808 + if (WARN_ON(ret))
1809 + return -EINVAL;
1810 + unicam->video_dev.tvnorms |= tvnorms;
1811 + }
1812 +
1813 + spin_lock_init(&unicam->dma_queue_lock);
1814 + mutex_init(&unicam->lock);
1815 +
1816 + /* Add controls from the subdevice */
1817 + ret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,
1818 + unicam->sensor->ctrl_handler, NULL);
1819 + if (ret < 0)
1820 + return ret;
1821 +
1822 + q = &unicam->buffer_queue;
1823 + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1824 + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1825 + q->drv_priv = unicam;
1826 + q->ops = &unicam_video_qops;
1827 + q->mem_ops = &vb2_dma_contig_memops;
1828 + q->buf_struct_size = sizeof(struct unicam_buffer);
1829 + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1830 + q->lock = &unicam->lock;
1831 + q->min_buffers_needed = 2;
1832 + q->dev = &unicam->pdev->dev;
1833 +
1834 + ret = vb2_queue_init(q);
1835 + if (ret) {
1836 + unicam_err(unicam, "vb2_queue_init() failed\n");
1837 + return ret;
1838 + }
1839 +
1840 + INIT_LIST_HEAD(&unicam->dma_queue.active);
1841 +
1842 + vdev = &unicam->video_dev;
1843 + strlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));
1844 + vdev->release = video_device_release_empty;
1845 + vdev->fops = &unicam_fops;
1846 + vdev->ioctl_ops = &unicam_ioctl_ops;
1847 + vdev->v4l2_dev = &unicam->v4l2_dev;
1848 + vdev->vfl_dir = VFL_DIR_RX;
1849 + vdev->queue = q;
1850 + vdev->lock = &unicam->lock;
1851 + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
1852 + V4L2_CAP_READWRITE;
1853 +
1854 + /* If the source has no controls then remove our ctrl handler. */
1855 + if (list_empty(&unicam->ctrl_handler.ctrls))
1856 + unicam->v4l2_dev.ctrl_handler = NULL;
1857 +
1858 + video_set_drvdata(vdev, unicam);
1859 + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
1860 + if (ret) {
1861 + unicam_err(unicam, "Unable to register video device.\n");
1862 + return ret;
1863 + }
1864 +
1865 + if (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
1866 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_STD);
1867 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_STD);
1868 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUMSTD);
1869 + }
1870 + if (!v4l2_subdev_has_op(unicam->sensor, video, querystd))
1871 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERYSTD);
1872 + if (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {
1873 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_EDID);
1874 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_EDID);
1875 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_DV_TIMINGS_CAP);
1876 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_DV_TIMINGS);
1877 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_DV_TIMINGS);
1878 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_DV_TIMINGS);
1879 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERY_DV_TIMINGS);
1880 + }
1881 +
1882 + ret = v4l2_device_register_subdev_nodes(&unicam->v4l2_dev);
1883 + if (ret) {
1884 + unicam_err(unicam,
1885 + "Unable to register subdev nodes.\n");
1886 + video_unregister_device(&unicam->video_dev);
1887 + return ret;
1888 + }
1889 +
1890 + return 0;
1891 +}
1892 +
1893 +static int unicam_async_complete(struct v4l2_async_notifier *notifier)
1894 +{
1895 + struct unicam_device *unicam = container_of(notifier->v4l2_dev,
1896 + struct unicam_device, v4l2_dev);
1897 +
1898 + return unicam_probe_complete(unicam);
1899 +}
1900 +
1901 +static const struct v4l2_async_notifier_operations unicam_async_ops = {
1902 + .bound = unicam_async_bound,
1903 + .complete = unicam_async_complete,
1904 +};
1905 +
1906 +static int of_unicam_connect_subdevs(struct unicam_device *dev)
1907 +{
1908 + struct platform_device *pdev = dev->pdev;
1909 + struct device_node *parent, *ep_node = NULL, *remote_ep = NULL,
1910 + *sensor_node = NULL;
1911 + struct v4l2_fwnode_endpoint *ep;
1912 + struct v4l2_async_subdev *asd;
1913 + struct v4l2_async_subdev **subdevs = NULL;
1914 + unsigned int peripheral_data_lanes;
1915 + int ret = -EINVAL;
1916 + unsigned int lane;
1917 +
1918 + parent = pdev->dev.of_node;
1919 +
1920 + asd = &dev->asd;
1921 + ep = &dev->endpoint;
1922 +
1923 + ep_node = of_graph_get_next_endpoint(parent, NULL);
1924 + if (!ep_node) {
1925 + unicam_dbg(3, dev, "can't get next endpoint\n");
1926 + goto cleanup_exit;
1927 + }
1928 +
1929 + unicam_dbg(3, dev, "ep_node is %s\n", ep_node->name);
1930 +
1931 + v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), ep);
1932 +
1933 + for (lane = 0; lane < ep->bus.mipi_csi2.num_data_lanes; lane++) {
1934 + if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
1935 + unicam_err(dev, "Local endpoint - data lane reordering not supported\n");
1936 + goto cleanup_exit;
1937 + }
1938 + }
1939 +
1940 + peripheral_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
1941 +
1942 + sensor_node = of_graph_get_remote_port_parent(ep_node);
1943 + if (!sensor_node) {
1944 + unicam_dbg(3, dev, "can't get remote parent\n");
1945 + goto cleanup_exit;
1946 + }
1947 + unicam_dbg(3, dev, "sensor_node is %s\n", sensor_node->name);
1948 + asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
1949 + asd->match.fwnode.fwnode = of_fwnode_handle(sensor_node);
1950 +
1951 + remote_ep = of_graph_get_remote_endpoint(ep_node);
1952 + if (!remote_ep) {
1953 + unicam_dbg(3, dev, "can't get remote-endpoint\n");
1954 + goto cleanup_exit;
1955 + }
1956 + unicam_dbg(3, dev, "remote_ep is %s\n", remote_ep->name);
1957 + v4l2_fwnode_endpoint_parse(of_fwnode_handle(remote_ep), ep);
1958 + unicam_dbg(3, dev, "parsed remote_ep to endpoint. nr_of_link_frequencies %u, bus_type %u\n",
1959 + ep->nr_of_link_frequencies, ep->bus_type);
1960 +
1961 + switch (ep->bus_type) {
1962 + case V4L2_MBUS_CSI2:
1963 + if (ep->bus.mipi_csi2.num_data_lanes >
1964 + peripheral_data_lanes) {
1965 + unicam_err(dev, "Subdevice %s wants too many data lanes (%u > %u)\n",
1966 + sensor_node->name,
1967 + ep->bus.mipi_csi2.num_data_lanes,
1968 + peripheral_data_lanes);
1969 + goto cleanup_exit;
1970 + }
1971 + for (lane = 0;
1972 + lane < ep->bus.mipi_csi2.num_data_lanes;
1973 + lane++) {
1974 + if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
1975 + unicam_err(dev, "Subdevice %s - incompatible data lane config\n",
1976 + sensor_node->name);
1977 + goto cleanup_exit;
1978 + }
1979 + }
1980 + dev->max_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
1981 + dev->bus_flags = ep->bus.mipi_csi2.flags;
1982 + break;
1983 + case V4L2_MBUS_CCP2:
1984 + if (ep->bus.mipi_csi1.clock_lane != 0 ||
1985 + ep->bus.mipi_csi1.data_lane != 1) {
1986 + unicam_err(dev, "Subdevice %s incompatible lane config\n",
1987 + sensor_node->name);
1988 + goto cleanup_exit;
1989 + }
1990 + dev->max_data_lanes = 1;
1991 + dev->bus_flags = ep->bus.mipi_csi1.strobe;
1992 + break;
1993 + default:
1994 + /* Unsupported bus type */
1995 + unicam_err(dev, "sub-device %s is not a CSI2 or CCP2 device %d\n",
1996 + sensor_node->name, ep->bus_type);
1997 + goto cleanup_exit;
1998 + }
1999 +
2000 + /* Store bus type - CSI2 or CCP2 */
2001 + dev->bus_type = ep->bus_type;
2002 + unicam_dbg(3, dev, "bus_type is %d\n", dev->bus_type);
2003 +
2004 + /* Store Virtual Channel number */
2005 + dev->virtual_channel = ep->base.id;
2006 +
2007 + unicam_dbg(3, dev, "v4l2-endpoint: %s\n",
2008 + dev->bus_type == V4L2_MBUS_CSI2 ? "CSI2" : "CCP2");
2009 + unicam_dbg(3, dev, "Virtual Channel=%d\n", dev->virtual_channel);
2010 + if (dev->bus_type == V4L2_MBUS_CSI2)
2011 + unicam_dbg(3, dev, "flags=0x%08x\n", ep->bus.mipi_csi2.flags);
2012 + unicam_dbg(3, dev, "num_data_lanes=%d\n", dev->max_data_lanes);
2013 +
2014 + unicam_dbg(1, dev, "found sub-device %s\n", sensor_node->name);
2015 +
2016 + subdevs = devm_kzalloc(&dev->pdev->dev, sizeof(*subdevs), GFP_KERNEL);
2017 + if (!subdevs) {
2018 + ret = -ENOMEM;
2019 + goto cleanup_exit;
2020 + }
2021 + subdevs[0] = asd;
2022 + dev->notifier.subdevs = subdevs;
2023 + dev->notifier.num_subdevs = 1;
2024 + dev->notifier.ops = &unicam_async_ops;
2025 + ret = v4l2_async_notifier_register(&dev->v4l2_dev,
2026 + &dev->notifier);
2027 + if (ret) {
2028 + unicam_err(dev, "Error registering async notifier - ret %d\n",
2029 + ret);
2030 + ret = -EINVAL;
2031 + }
2032 +
2033 +cleanup_exit:
2034 + if (remote_ep)
2035 + of_node_put(remote_ep);
2036 + if (sensor_node)
2037 + of_node_put(sensor_node);
2038 + if (ep_node)
2039 + of_node_put(ep_node);
2040 +
2041 + return ret;
2042 +}
2043 +
2044 +static int unicam_probe(struct platform_device *pdev)
2045 +{
2046 + struct unicam_cfg *unicam_cfg;
2047 + struct unicam_device *unicam;
2048 + struct v4l2_ctrl_handler *hdl;
2049 + struct resource *res;
2050 + int ret;
2051 +
2052 + unicam = devm_kzalloc(&pdev->dev, sizeof(*unicam), GFP_KERNEL);
2053 + if (!unicam)
2054 + return -ENOMEM;
2055 +
2056 + unicam->pdev = pdev;
2057 + unicam_cfg = &unicam->cfg;
2058 +
2059 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2060 + unicam_cfg->base = devm_ioremap_resource(&pdev->dev, res);
2061 + if (IS_ERR(unicam_cfg->base)) {
2062 + unicam_err(unicam, "Failed to get main io block\n");
2063 + return PTR_ERR(unicam_cfg->base);
2064 + }
2065 +
2066 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2067 + unicam_cfg->clk_gate_base = devm_ioremap_resource(&pdev->dev, res);
2068 + if (IS_ERR(unicam_cfg->clk_gate_base)) {
2069 + unicam_err(unicam, "Failed to get 2nd io block\n");
2070 + return PTR_ERR(unicam_cfg->clk_gate_base);
2071 + }
2072 +
2073 + unicam->clock = devm_clk_get(&pdev->dev, "lp");
2074 + if (IS_ERR(unicam->clock)) {
2075 + unicam_err(unicam, "Failed to get clock\n");
2076 + return PTR_ERR(unicam->clock);
2077 + }
2078 +
2079 + ret = platform_get_irq(pdev, 0);
2080 + if (ret <= 0) {
2081 + dev_err(&pdev->dev, "No IRQ resource\n");
2082 + return -ENODEV;
2083 + }
2084 +
2085 + ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
2086 + "unicam_capture0", unicam);
2087 + if (ret) {
2088 + dev_err(&pdev->dev, "Unable to request interrupt\n");
2089 + return -EINVAL;
2090 + }
2091 +
2092 + ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
2093 + if (ret) {
2094 + unicam_err(unicam,
2095 + "Unable to register v4l2 device.\n");
2096 + return ret;
2097 + }
2098 +
2099 + /* Reserve space for the controls */
2100 + hdl = &unicam->ctrl_handler;
2101 + ret = v4l2_ctrl_handler_init(hdl, 16);
2102 + if (ret < 0)
2103 + goto probe_out_v4l2_unregister;
2104 + unicam->v4l2_dev.ctrl_handler = hdl;
2105 +
2106 + /* set the driver data in platform device */
2107 + platform_set_drvdata(pdev, unicam);
2108 +
2109 + ret = of_unicam_connect_subdevs(unicam);
2110 + if (ret) {
2111 + dev_err(&pdev->dev, "Failed to connect subdevs\n");
2112 + goto free_hdl;
2113 + }
2114 +
2115 + /* Enable the block power domain */
2116 + pm_runtime_enable(&pdev->dev);
2117 +
2118 + return 0;
2119 +
2120 +free_hdl:
2121 + v4l2_ctrl_handler_free(hdl);
2122 +probe_out_v4l2_unregister:
2123 + v4l2_device_unregister(&unicam->v4l2_dev);
2124 + return ret;
2125 +}
2126 +
2127 +static int unicam_remove(struct platform_device *pdev)
2128 +{
2129 + struct unicam_device *unicam = platform_get_drvdata(pdev);
2130 +
2131 + unicam_dbg(2, unicam, "%s\n", __func__);
2132 +
2133 + pm_runtime_disable(&pdev->dev);
2134 +
2135 + v4l2_async_notifier_unregister(&unicam->notifier);
2136 + v4l2_ctrl_handler_free(&unicam->ctrl_handler);
2137 + v4l2_device_unregister(&unicam->v4l2_dev);
2138 + video_unregister_device(&unicam->video_dev);
2139 + if (unicam->sensor_config)
2140 + v4l2_subdev_free_pad_config(unicam->sensor_config);
2141 +
2142 + return 0;
2143 +}
2144 +
2145 +static const struct of_device_id unicam_of_match[] = {
2146 + { .compatible = "brcm,bcm2835-unicam", },
2147 + { /* sentinel */ },
2148 +};
2149 +MODULE_DEVICE_TABLE(of, unicam_of_match);
2150 +
2151 +static struct platform_driver unicam_driver = {
2152 + .probe = unicam_probe,
2153 + .remove = unicam_remove,
2154 + .driver = {
2155 + .name = UNICAM_MODULE_NAME,
2156 + .of_match_table = of_match_ptr(unicam_of_match),
2157 + },
2158 +};
2159 +
2160 +module_platform_driver(unicam_driver);
2161 +
2162 +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.org>");
2163 +MODULE_DESCRIPTION("BCM2835 Unicam driver");
2164 +MODULE_LICENSE("GPL");
2165 +MODULE_VERSION(UNICAM_VERSION);
2166 --- /dev/null
2167 +++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
2168 @@ -0,0 +1,264 @@
2169 +/*
2170 + * Copyright (C) 2017 Raspberry Pi Trading.
2171 + * Dave Stevenson <dave.stevenson@raspberrypi.org>
2172 + *
2173 + * This program is free software; you can redistribute it and/or modify
2174 + * it under the terms of the GNU General Public License version 2 as
2175 + * published by the Free Software Foundation.
2176 + *
2177 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2178 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
2179 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2180 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
2181 + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
2182 + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
2183 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2184 + * SOFTWARE.
2185 + */
2186 +
2187 +#ifndef VC4_REGS_UNICAM_H
2188 +#define VC4_REGS_UNICAM_H
2189 +
2190 +/*
2191 + * The following values are taken from files found within the code drop
2192 + * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
2193 + * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
2194 + * They have been modified to be only the register offset.
2195 + */
2196 +#define UNICAM_CTRL 0x000
2197 +#define UNICAM_STA 0x004
2198 +#define UNICAM_ANA 0x008
2199 +#define UNICAM_PRI 0x00c
2200 +#define UNICAM_CLK 0x010
2201 +#define UNICAM_CLT 0x014
2202 +#define UNICAM_DAT0 0x018
2203 +#define UNICAM_DAT1 0x01c
2204 +#define UNICAM_DAT2 0x020
2205 +#define UNICAM_DAT3 0x024
2206 +#define UNICAM_DLT 0x028
2207 +#define UNICAM_CMP0 0x02c
2208 +#define UNICAM_CMP1 0x030
2209 +#define UNICAM_CAP0 0x034
2210 +#define UNICAM_CAP1 0x038
2211 +#define UNICAM_ICTL 0x100
2212 +#define UNICAM_ISTA 0x104
2213 +#define UNICAM_IDI0 0x108
2214 +#define UNICAM_IPIPE 0x10c
2215 +#define UNICAM_IBSA0 0x110
2216 +#define UNICAM_IBEA0 0x114
2217 +#define UNICAM_IBLS 0x118
2218 +#define UNICAM_IBWP 0x11c
2219 +#define UNICAM_IHWIN 0x120
2220 +#define UNICAM_IHSTA 0x124
2221 +#define UNICAM_IVWIN 0x128
2222 +#define UNICAM_IVSTA 0x12c
2223 +#define UNICAM_ICC 0x130
2224 +#define UNICAM_ICS 0x134
2225 +#define UNICAM_IDC 0x138
2226 +#define UNICAM_IDPO 0x13c
2227 +#define UNICAM_IDCA 0x140
2228 +#define UNICAM_IDCD 0x144
2229 +#define UNICAM_IDS 0x148
2230 +#define UNICAM_DCS 0x200
2231 +#define UNICAM_DBSA0 0x204
2232 +#define UNICAM_DBEA0 0x208
2233 +#define UNICAM_DBWP 0x20c
2234 +#define UNICAM_DBCTL 0x300
2235 +#define UNICAM_IBSA1 0x304
2236 +#define UNICAM_IBEA1 0x308
2237 +#define UNICAM_IDI1 0x30c
2238 +#define UNICAM_DBSA1 0x310
2239 +#define UNICAM_DBEA1 0x314
2240 +#define UNICAM_MISC 0x400
2241 +
2242 +/*
2243 + * The following bitmasks are from the kernel released by Broadcom
2244 + * for Android - https://android.googlesource.com/kernel/bcm/
2245 + * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
2246 + * Unicam block as BCM2835, as defined in eg
2247 + * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
2248 + * Values reworked to use the kernel BIT and GENMASK macros.
2249 + *
2250 + * Some of the bit mnenomics have been amended to match the datasheet.
2251 + */
2252 +/* UNICAM_CTRL Register */
2253 +#define UNICAM_CPE BIT(0)
2254 +#define UNICAM_MEM BIT(1)
2255 +#define UNICAM_CPR BIT(2)
2256 +#define UNICAM_CPM_MASK GENMASK(3, 3)
2257 +#define UNICAM_CPM_CSI2 0
2258 +#define UNICAM_CPM_CCP2 1
2259 +#define UNICAM_SOE BIT(4)
2260 +#define UNICAM_DCM_MASK GENMASK(5, 5)
2261 +#define UNICAM_DCM_STROBE 0
2262 +#define UNICAM_DCM_DATA 1
2263 +#define UNICAM_SLS BIT(6)
2264 +#define UNICAM_PFT_MASK GENMASK(11, 8)
2265 +#define UNICAM_OET_MASK GENMASK(20, 12)
2266 +
2267 +/* UNICAM_STA Register */
2268 +#define UNICAM_SYN BIT(0)
2269 +#define UNICAM_CS BIT(1)
2270 +#define UNICAM_SBE BIT(2)
2271 +#define UNICAM_PBE BIT(3)
2272 +#define UNICAM_HOE BIT(4)
2273 +#define UNICAM_PLE BIT(5)
2274 +#define UNICAM_SSC BIT(6)
2275 +#define UNICAM_CRCE BIT(7)
2276 +#define UNICAM_OES BIT(8)
2277 +#define UNICAM_IFO BIT(9)
2278 +#define UNICAM_OFO BIT(10)
2279 +#define UNICAM_BFO BIT(11)
2280 +#define UNICAM_DL BIT(12)
2281 +#define UNICAM_PS BIT(13)
2282 +#define UNICAM_IS BIT(14)
2283 +#define UNICAM_PI0 BIT(15)
2284 +#define UNICAM_PI1 BIT(16)
2285 +#define UNICAM_FSI_S BIT(17)
2286 +#define UNICAM_FEI_S BIT(18)
2287 +#define UNICAM_LCI_S BIT(19)
2288 +#define UNICAM_BUF0_RDY BIT(20)
2289 +#define UNICAM_BUF0_NO BIT(21)
2290 +#define UNICAM_BUF1_RDY BIT(22)
2291 +#define UNICAM_BUF1_NO BIT(23)
2292 +#define UNICAM_DI BIT(24)
2293 +
2294 +#define UNICAM_STA_MASK_ALL \
2295 + (UNICAM_DL + \
2296 + UNICAM_SBE + \
2297 + UNICAM_PBE + \
2298 + UNICAM_HOE + \
2299 + UNICAM_PLE + \
2300 + UNICAM_SSC + \
2301 + UNICAM_CRCE + \
2302 + UNICAM_IFO + \
2303 + UNICAM_OFO + \
2304 + UNICAM_PS + \
2305 + UNICAM_PI0 + \
2306 + UNICAM_PI1)
2307 +
2308 +/* UNICAM_ANA Register */
2309 +#define UNICAM_APD BIT(0)
2310 +#define UNICAM_BPD BIT(1)
2311 +#define UNICAM_AR BIT(2)
2312 +#define UNICAM_DDL BIT(3)
2313 +#define UNICAM_CTATADJ_MASK GENMASK(7, 4)
2314 +#define UNICAM_PTATADJ_MASK GENMASK(11, 8)
2315 +
2316 +/* UNICAM_PRI Register */
2317 +#define UNICAM_PE BIT(0)
2318 +#define UNICAM_PT_MASK GENMASK(2, 1)
2319 +#define UNICAM_NP_MASK GENMASK(7, 4)
2320 +#define UNICAM_PP_MASK GENMASK(11, 8)
2321 +#define UNICAM_BS_MASK GENMASK(15, 12)
2322 +#define UNICAM_BL_MASK GENMASK(17, 16)
2323 +
2324 +/* UNICAM_CLK Register */
2325 +#define UNICAM_CLE BIT(0)
2326 +#define UNICAM_CLPD BIT(1)
2327 +#define UNICAM_CLLPE BIT(2)
2328 +#define UNICAM_CLHSE BIT(3)
2329 +#define UNICAM_CLTRE BIT(4)
2330 +#define UNICAM_CLAC_MASK GENMASK(8, 5)
2331 +#define UNICAM_CLSTE BIT(29)
2332 +
2333 +/* UNICAM_CLT Register */
2334 +#define UNICAM_CLT1_MASK GENMASK(7, 0)
2335 +#define UNICAM_CLT2_MASK GENMASK(15, 8)
2336 +
2337 +/* UNICAM_DATn Registers */
2338 +#define UNICAM_DLE BIT(0)
2339 +#define UNICAM_DLPD BIT(1)
2340 +#define UNICAM_DLLPE BIT(2)
2341 +#define UNICAM_DLHSE BIT(3)
2342 +#define UNICAM_DLTRE BIT(4)
2343 +#define UNICAM_DLSM BIT(5)
2344 +#define UNICAM_DLFO BIT(28)
2345 +#define UNICAM_DLSTE BIT(29)
2346 +
2347 +#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
2348 +
2349 +/* UNICAM_DLT Register */
2350 +#define UNICAM_DLT1_MASK GENMASK(7, 0)
2351 +#define UNICAM_DLT2_MASK GENMASK(15, 8)
2352 +#define UNICAM_DLT3_MASK GENMASK(23, 16)
2353 +
2354 +/* UNICAM_ICTL Register */
2355 +#define UNICAM_FSIE BIT(0)
2356 +#define UNICAM_FEIE BIT(1)
2357 +#define UNICAM_IBOB BIT(2)
2358 +#define UNICAM_FCM BIT(3)
2359 +#define UNICAM_TFC BIT(4)
2360 +#define UNICAM_LIP_MASK GENMASK(6, 5)
2361 +#define UNICAM_LCIE_MASK GENMASK(28, 16)
2362 +
2363 +/* UNICAM_IDI0/1 Register */
2364 +#define UNICAM_ID0_MASK GENMASK(7, 0)
2365 +#define UNICAM_ID1_MASK GENMASK(15, 8)
2366 +#define UNICAM_ID2_MASK GENMASK(23, 16)
2367 +#define UNICAM_ID3_MASK GENMASK(31, 24)
2368 +
2369 +/* UNICAM_ISTA Register */
2370 +#define UNICAM_FSI BIT(0)
2371 +#define UNICAM_FEI BIT(1)
2372 +#define UNICAM_LCI BIT(2)
2373 +
2374 +#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
2375 +
2376 +/* UNICAM_IPIPE Register */
2377 +#define UNICAM_PUM_MASK GENMASK(2, 0)
2378 + /* Unpacking modes */
2379 + #define UNICAM_PUM_NONE 0
2380 + #define UNICAM_PUM_UNPACK6 1
2381 + #define UNICAM_PUM_UNPACK7 2
2382 + #define UNICAM_PUM_UNPACK8 3
2383 + #define UNICAM_PUM_UNPACK10 4
2384 + #define UNICAM_PUM_UNPACK12 5
2385 + #define UNICAM_PUM_UNPACK14 6
2386 + #define UNICAM_PUM_UNPACK16 7
2387 +#define UNICAM_DDM_MASK GENMASK(6, 3)
2388 +#define UNICAM_PPM_MASK GENMASK(9, 7)
2389 + /* Packing modes */
2390 + #define UNICAM_PPM_NONE 0
2391 + #define UNICAM_PPM_PACK8 1
2392 + #define UNICAM_PPM_PACK10 2
2393 + #define UNICAM_PPM_PACK12 3
2394 + #define UNICAM_PPM_PACK14 4
2395 + #define UNICAM_PPM_PACK16 5
2396 +#define UNICAM_DEM_MASK GENMASK(11, 10)
2397 +#define UNICAM_DEBL_MASK GENMASK(14, 12)
2398 +#define UNICAM_ICM_MASK GENMASK(16, 15)
2399 +#define UNICAM_IDM_MASK GENMASK(17, 17)
2400 +
2401 +/* UNICAM_ICC Register */
2402 +#define UNICAM_ICFL_MASK GENMASK(4, 0)
2403 +#define UNICAM_ICFH_MASK GENMASK(9, 5)
2404 +#define UNICAM_ICST_MASK GENMASK(12, 10)
2405 +#define UNICAM_ICLT_MASK GENMASK(15, 13)
2406 +#define UNICAM_ICLL_MASK GENMASK(31, 16)
2407 +
2408 +/* UNICAM_DCS Register */
2409 +#define UNICAM_DIE BIT(0)
2410 +#define UNICAM_DIM BIT(1)
2411 +#define UNICAM_DBOB BIT(3)
2412 +#define UNICAM_FDE BIT(4)
2413 +#define UNICAM_LDP BIT(5)
2414 +#define UNICAM_EDL_MASK GENMASK(15, 8)
2415 +
2416 +/* UNICAM_DBCTL Register */
2417 +#define UNICAM_DBEN BIT(0)
2418 +#define UNICAM_BUF0_IE BIT(1)
2419 +#define UNICAM_BUF1_IE BIT(2)
2420 +
2421 +/* UNICAM_CMP[0,1] register */
2422 +#define UNICAM_PCE BIT(31)
2423 +#define UNICAM_GI BIT(9)
2424 +#define UNICAM_CPH BIT(8)
2425 +#define UNICAM_PCVC_MASK GENMASK(7, 6)
2426 +#define UNICAM_PCDT_MASK GENMASK(5, 0)
2427 +
2428 +/* UNICAM_MISC register */
2429 +#define UNICAM_FL0 BIT(6)
2430 +#define UNICAM_FL1 BIT(9)
2431 +
2432 +#endif
Staging tree of Daniel Golle