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1 From c2e579662748cb5d3bf3e31f58d99c4db4d102c1 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:22:36 +0800
4 Subject: [PATCH 08/25] clk: mtmips: add clock driver for MediaTek MT7621 SoC
5
6 This patch adds a clock driver for MediaTek MT7621 SoC.
7 This driver provides clock gate control as well as getting clock frequency
8 for CPU/SYS/XTAL and some peripherals.
9
10 Reviewed-by: Sean Anderson <seanga2@gmail.com>
11 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
12 ---
13 drivers/clk/mtmips/Makefile | 1 +
14 drivers/clk/mtmips/clk-mt7621.c | 288 +++++++++++++++++++++++++
15 include/dt-bindings/clock/mt7621-clk.h | 46 ++++
16 3 files changed, 335 insertions(+)
17 create mode 100644 drivers/clk/mtmips/clk-mt7621.c
18 create mode 100644 include/dt-bindings/clock/mt7621-clk.h
19
20 diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile
21 index 732e7f2545..ee8b5afe87 100644
22 --- a/drivers/clk/mtmips/Makefile
23 +++ b/drivers/clk/mtmips/Makefile
24 @@ -1,4 +1,5 @@
25 # SPDX-License-Identifier: GPL-2.0
26
27 obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
28 +obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
29 obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
30 diff --git a/drivers/clk/mtmips/clk-mt7621.c b/drivers/clk/mtmips/clk-mt7621.c
31 new file mode 100644
32 index 0000000000..03363b70d7
33 --- /dev/null
34 +++ b/drivers/clk/mtmips/clk-mt7621.c
35 @@ -0,0 +1,288 @@
36 +// SPDX-License-Identifier: GPL-2.0
37 +/*
38 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
39 + *
40 + * Author: Weijie Gao <weijie.gao@mediatek.com>
41 + */
42 +
43 +#include <clk-uclass.h>
44 +#include <dm.h>
45 +#include <dm/device_compat.h>
46 +#include <regmap.h>
47 +#include <syscon.h>
48 +#include <dt-bindings/clock/mt7621-clk.h>
49 +#include <linux/io.h>
50 +#include <linux/bitops.h>
51 +#include <linux/bitfield.h>
52 +
53 +#define SYSC_MAP_SIZE 0x100
54 +#define MEMC_MAP_SIZE 0x1000
55 +
56 +/* SYSC */
57 +#define SYSCFG0_REG 0x10
58 +#define XTAL_MODE_SEL GENMASK(8, 6)
59 +
60 +#define CLKCFG0_REG 0x2c
61 +#define CPU_CLK_SEL GENMASK(31, 30)
62 +#define PERI_CLK_SEL BIT(4)
63 +
64 +#define CLKCFG1_REG 0x30
65 +
66 +#define CUR_CLK_STS_REG 0x44
67 +#define CUR_CPU_FDIV GENMASK(12, 8)
68 +#define CUR_CPU_FFRAC GENMASK(4, 0)
69 +
70 +/* MEMC */
71 +#define MEMPLL1_REG 0x0604
72 +#define RG_MEPL_DIV2_SEL GENMASK(2, 1)
73 +
74 +#define MEMPLL6_REG 0x0618
75 +#define MEMPLL18_REG 0x0648
76 +#define RG_MEPL_PREDIV GENMASK(13, 12)
77 +#define RG_MEPL_FBDIV GENMASK(10, 4)
78 +
79 +/* Fixed 500M clock */
80 +#define GMPLL_CLK 500000000
81 +
82 +struct mt7621_clk_priv {
83 + void __iomem *sysc_base;
84 + int cpu_clk;
85 + int ddr_clk;
86 + int sys_clk;
87 + int xtal_clk;
88 +};
89 +
90 +enum mt7621_clk_src {
91 + CLK_SRC_CPU,
92 + CLK_SRC_DDR,
93 + CLK_SRC_SYS,
94 + CLK_SRC_XTAL,
95 + CLK_SRC_PERI,
96 + CLK_SRC_125M,
97 + CLK_SRC_150M,
98 + CLK_SRC_250M,
99 + CLK_SRC_270M,
100 +
101 + __CLK_SRC_MAX
102 +};
103 +
104 +struct mt7621_clk_map {
105 + u32 cgbit;
106 + enum mt7621_clk_src clksrc;
107 +};
108 +
109 +#define CLK_MAP(_id, _cg, _src) \
110 + [_id] = { .cgbit = (_cg), .clksrc = (_src) }
111 +
112 +#define CLK_MAP_SRC(_id, _src) \
113 + [_id] = { .cgbit = UINT32_MAX, .clksrc = (_src) }
114 +
115 +static const struct mt7621_clk_map mt7621_clk_mappings[] = {
116 + CLK_MAP_SRC(MT7621_CLK_XTAL, CLK_SRC_XTAL),
117 + CLK_MAP_SRC(MT7621_CLK_CPU, CLK_SRC_CPU),
118 + CLK_MAP_SRC(MT7621_CLK_BUS, CLK_SRC_SYS),
119 + CLK_MAP_SRC(MT7621_CLK_50M, CLK_SRC_PERI),
120 + CLK_MAP_SRC(MT7621_CLK_125M, CLK_SRC_125M),
121 + CLK_MAP_SRC(MT7621_CLK_150M, CLK_SRC_150M),
122 + CLK_MAP_SRC(MT7621_CLK_250M, CLK_SRC_250M),
123 + CLK_MAP_SRC(MT7621_CLK_270M, CLK_SRC_270M),
124 +
125 + CLK_MAP(MT7621_CLK_HSDMA, 5, CLK_SRC_150M),
126 + CLK_MAP(MT7621_CLK_FE, 6, CLK_SRC_250M),
127 + CLK_MAP(MT7621_CLK_SP_DIVTX, 7, CLK_SRC_270M),
128 + CLK_MAP(MT7621_CLK_TIMER, 8, CLK_SRC_PERI),
129 + CLK_MAP(MT7621_CLK_PCM, 11, CLK_SRC_270M),
130 + CLK_MAP(MT7621_CLK_PIO, 13, CLK_SRC_PERI),
131 + CLK_MAP(MT7621_CLK_GDMA, 14, CLK_SRC_SYS),
132 + CLK_MAP(MT7621_CLK_NAND, 15, CLK_SRC_125M),
133 + CLK_MAP(MT7621_CLK_I2C, 16, CLK_SRC_PERI),
134 + CLK_MAP(MT7621_CLK_I2S, 17, CLK_SRC_270M),
135 + CLK_MAP(MT7621_CLK_SPI, 18, CLK_SRC_SYS),
136 + CLK_MAP(MT7621_CLK_UART1, 19, CLK_SRC_PERI),
137 + CLK_MAP(MT7621_CLK_UART2, 20, CLK_SRC_PERI),
138 + CLK_MAP(MT7621_CLK_UART3, 21, CLK_SRC_PERI),
139 + CLK_MAP(MT7621_CLK_ETH, 23, CLK_SRC_PERI),
140 + CLK_MAP(MT7621_CLK_PCIE0, 24, CLK_SRC_125M),
141 + CLK_MAP(MT7621_CLK_PCIE1, 25, CLK_SRC_125M),
142 + CLK_MAP(MT7621_CLK_PCIE2, 26, CLK_SRC_125M),
143 + CLK_MAP(MT7621_CLK_CRYPTO, 29, CLK_SRC_250M),
144 + CLK_MAP(MT7621_CLK_SHXC, 30, CLK_SRC_PERI),
145 +
146 + CLK_MAP_SRC(MT7621_CLK_MAX, __CLK_SRC_MAX),
147 +
148 + CLK_MAP_SRC(MT7621_CLK_DDR, CLK_SRC_DDR),
149 +};
150 +
151 +static ulong mt7621_clk_get_rate(struct clk *clk)
152 +{
153 + struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
154 + u32 val;
155 +
156 + switch (mt7621_clk_mappings[clk->id].clksrc) {
157 + case CLK_SRC_CPU:
158 + return priv->cpu_clk;
159 + case CLK_SRC_DDR:
160 + return priv->ddr_clk;
161 + case CLK_SRC_SYS:
162 + return priv->sys_clk;
163 + case CLK_SRC_XTAL:
164 + return priv->xtal_clk;
165 + case CLK_SRC_PERI:
166 + val = readl(priv->sysc_base + CLKCFG0_REG);
167 + if (val & PERI_CLK_SEL)
168 + return priv->xtal_clk;
169 + else
170 + return GMPLL_CLK / 10;
171 + case CLK_SRC_125M:
172 + return 125000000;
173 + case CLK_SRC_150M:
174 + return 150000000;
175 + case CLK_SRC_250M:
176 + return 250000000;
177 + case CLK_SRC_270M:
178 + return 270000000;
179 + default:
180 + return 0;
181 + }
182 +}
183 +
184 +static int mt7621_clk_enable(struct clk *clk)
185 +{
186 + struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
187 + u32 cgbit;
188 +
189 + cgbit = mt7621_clk_mappings[clk->id].cgbit;
190 + if (cgbit == UINT32_MAX)
191 + return -ENOSYS;
192 +
193 + setbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
194 +
195 + return 0;
196 +}
197 +
198 +static int mt7621_clk_disable(struct clk *clk)
199 +{
200 + struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
201 + u32 cgbit;
202 +
203 + cgbit = mt7621_clk_mappings[clk->id].cgbit;
204 + if (cgbit == UINT32_MAX)
205 + return -ENOSYS;
206 +
207 + clrbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
208 +
209 + return 0;
210 +}
211 +
212 +static int mt7621_clk_request(struct clk *clk)
213 +{
214 + if (clk->id >= ARRAY_SIZE(mt7621_clk_mappings))
215 + return -EINVAL;
216 + return 0;
217 +}
218 +
219 +const struct clk_ops mt7621_clk_ops = {
220 + .request = mt7621_clk_request,
221 + .enable = mt7621_clk_enable,
222 + .disable = mt7621_clk_disable,
223 + .get_rate = mt7621_clk_get_rate,
224 +};
225 +
226 +static void mt7621_get_clocks(struct mt7621_clk_priv *priv, struct regmap *memc)
227 +{
228 + u32 bs, xtal_sel, clkcfg0, cur_clk, mempll, dividx, fb;
229 + u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk;
230 + static const u32 xtal_div_tbl[] = {0, 1, 2, 2};
231 +
232 + bs = readl(priv->sysc_base + SYSCFG0_REG);
233 + clkcfg0 = readl(priv->sysc_base + CLKCFG0_REG);
234 + cur_clk = readl(priv->sysc_base + CUR_CLK_STS_REG);
235 +
236 + xtal_sel = FIELD_GET(XTAL_MODE_SEL, bs);
237 +
238 + if (xtal_sel <= 2)
239 + xtal_clk = 20 * 1000 * 1000;
240 + else if (xtal_sel <= 5)
241 + xtal_clk = 40 * 1000 * 1000;
242 + else
243 + xtal_clk = 25 * 1000 * 1000;
244 +
245 + switch (FIELD_GET(CPU_CLK_SEL, clkcfg0)) {
246 + case 0:
247 + cpu_clk = GMPLL_CLK;
248 + break;
249 + case 1:
250 + regmap_read(memc, MEMPLL18_REG, &mempll);
251 + dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
252 + fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
253 + xtal_div = 1 << xtal_div_tbl[dividx];
254 + cpu_clk = (fb + 1) * xtal_clk / xtal_div;
255 + break;
256 + default:
257 + cpu_clk = xtal_clk;
258 + }
259 +
260 + ffiv = FIELD_GET(CUR_CPU_FDIV, cur_clk);
261 + ffrac = FIELD_GET(CUR_CPU_FFRAC, cur_clk);
262 + cpu_clk = cpu_clk / ffiv * ffrac;
263 +
264 + regmap_read(memc, MEMPLL6_REG, &mempll);
265 + dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
266 + fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
267 + xtal_div = 1 << xtal_div_tbl[dividx];
268 + ddr_clk = fb * xtal_clk / xtal_div;
269 +
270 + regmap_read(memc, MEMPLL1_REG, &bs);
271 + if (!FIELD_GET(RG_MEPL_DIV2_SEL, bs))
272 + ddr_clk *= 2;
273 +
274 + priv->cpu_clk = cpu_clk;
275 + priv->sys_clk = cpu_clk / 4;
276 + priv->ddr_clk = ddr_clk;
277 + priv->xtal_clk = xtal_clk;
278 +}
279 +
280 +static int mt7621_clk_probe(struct udevice *dev)
281 +{
282 + struct mt7621_clk_priv *priv = dev_get_priv(dev);
283 + struct ofnode_phandle_args args;
284 + struct udevice *pdev;
285 + struct regmap *memc;
286 + int ret;
287 +
288 + pdev = dev_get_parent(dev);
289 + if (!pdev)
290 + return -ENODEV;
291 +
292 + priv->sysc_base = dev_remap_addr(pdev);
293 + if (!priv->sysc_base)
294 + return -EINVAL;
295 +
296 + /* get corresponding memc phandle */
297 + ret = dev_read_phandle_with_args(dev, "mediatek,memc", NULL, 0, 0,
298 + &args);
299 + if (ret)
300 + return ret;
301 +
302 + memc = syscon_node_to_regmap(args.node);
303 + if (IS_ERR(memc))
304 + return PTR_ERR(memc);
305 +
306 + mt7621_get_clocks(priv, memc);
307 +
308 + return 0;
309 +}
310 +
311 +static const struct udevice_id mt7621_clk_ids[] = {
312 + { .compatible = "mediatek,mt7621-clk" },
313 + { }
314 +};
315 +
316 +U_BOOT_DRIVER(mt7621_clk) = {
317 + .name = "mt7621-clk",
318 + .id = UCLASS_CLK,
319 + .of_match = mt7621_clk_ids,
320 + .probe = mt7621_clk_probe,
321 + .priv_auto = sizeof(struct mt7621_clk_priv),
322 + .ops = &mt7621_clk_ops,
323 +};
324 diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
325 new file mode 100644
326 index 0000000000..978c67951b
327 --- /dev/null
328 +++ b/include/dt-bindings/clock/mt7621-clk.h
329 @@ -0,0 +1,46 @@
330 +/* SPDX-License-Identifier: GPL-2.0 */
331 +/*
332 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
333 + *
334 + * Author: Weijie Gao <weijie.gao@mediatek.com>
335 + */
336 +
337 +#ifndef _DT_BINDINGS_MT7621_CLK_H_
338 +#define _DT_BINDINGS_MT7621_CLK_H_
339 +
340 +#define MT7621_CLK_XTAL 0
341 +#define MT7621_CLK_CPU 1
342 +#define MT7621_CLK_BUS 2
343 +#define MT7621_CLK_50M 3
344 +#define MT7621_CLK_125M 4
345 +#define MT7621_CLK_150M 5
346 +#define MT7621_CLK_250M 6
347 +#define MT7621_CLK_270M 7
348 +
349 +#define MT7621_CLK_HSDMA 8
350 +#define MT7621_CLK_FE 9
351 +#define MT7621_CLK_SP_DIVTX 10
352 +#define MT7621_CLK_TIMER 11
353 +#define MT7621_CLK_PCM 12
354 +#define MT7621_CLK_PIO 13
355 +#define MT7621_CLK_GDMA 14
356 +#define MT7621_CLK_NAND 15
357 +#define MT7621_CLK_I2C 16
358 +#define MT7621_CLK_I2S 17
359 +#define MT7621_CLK_SPI 18
360 +#define MT7621_CLK_UART1 19
361 +#define MT7621_CLK_UART2 20
362 +#define MT7621_CLK_UART3 21
363 +#define MT7621_CLK_ETH 22
364 +#define MT7621_CLK_PCIE0 23
365 +#define MT7621_CLK_PCIE1 24
366 +#define MT7621_CLK_PCIE2 25
367 +#define MT7621_CLK_CRYPTO 26
368 +#define MT7621_CLK_SHXC 27
369 +
370 +#define MT7621_CLK_MAX 28
371 +
372 +/* for u-boot only */
373 +#define MT7621_CLK_DDR 29
374 +
375 +#endif /* _DT_BINDINGS_MT7621_CLK_H_ */
376 --
377 2.36.1
378
Staging tree of Sander Vanheule