git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From fa4d4ed28c92cf4470e518f1a7362dc7941632d7 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Wed, 28 Jun 2023 16:24:29 +0100
   4 Subject: [PATCH] irqchip/irq-brcmstb-l2: Add config for 2711 controller
   5
   6 We currently see these regularly:
   7 [   25.157560] irq 31, desc: 00000000c15e6d2c, depth: 0, count: 0, unhandled: 0
   8 [   25.164658] ->handle_irq():  00000000b1775675, brcmstb_l2_intc_irq_handle+0x0/0x1a8
   9 [   25.172352] ->irq_data.chip(): 00000000fea59f1c, gic_chip_mode1+0x0/0x108
  10 [   25.179166] ->action(): 000000003eda6d6f
  11 [   25.183096] ->action->handler(): 000000002c09e646, bad_chained_irq+0x0/0x58
  12 [   25.190084]      IRQ_LEVEL set
  13 [   25.193142]    IRQ_NOPROBE set
  14 [   25.196198]  IRQ_NOREQUEST set
  15 [   25.199255]   IRQ_NOTHREAD set
  16
  17 with:
  18 $ cat /proc/interrupts  | grep 31:
  19  31:          1          0          0          0     GICv2 129 Level     (null)
  20
  21 The interrupt is described in DT with IRQ_TYPE_LEVEL_HIGH
  22
  23 But the current compatible string uses the controller in edge triggered mode
  24 (as that config matches our register layout).
  25
  26 Add a new compatible structure for level driven interrupt with our register layout.
  27
  28 We had already been using this compatible string in device tree, so no change needed
  29 there.
  30
  31 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  32 ---
  33  drivers/irqchip/irq-brcmstb-l2.c | 17 +++++++++++++++++
  34  1 file changed, 17 insertions(+)
  35
  36 --- a/drivers/irqchip/irq-brcmstb-l2.c
  37 +++ b/drivers/irqchip/irq-brcmstb-l2.c
  38 @@ -52,6 +52,16 @@ static const struct brcmstb_intc_init_pa
  39         .cpu_mask_clear         = 0x0C
  40  };
  41
  42 +/* Register offsets in the 2711 L2 level interrupt controller */
  43 +static const struct brcmstb_intc_init_params l2_2711_lvl_intc_init = {
  44 +       .handler                = handle_level_irq,
  45 +       .cpu_status             = 0x00,
  46 +       .cpu_clear              = 0x08,
  47 +       .cpu_mask_status        = 0x0c,
  48 +       .cpu_mask_set           = 0x10,
  49 +       .cpu_mask_clear         = 0x14
  50 +};
  51 +
  52  /* L2 intc private data structure */
  53  struct brcmstb_l2_intc_data {
  54         struct irq_domain *domain;
  55 @@ -289,11 +299,18 @@ static int __init brcmstb_l2_lvl_intc_of
  56         return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
  57  }
  58
  59 +static int __init brcmstb_l2_2711_lvl_intc_of_init(struct device_node *np,
  60 +       struct device_node *parent)
  61 +{
  62 +       return brcmstb_l2_intc_of_init(np, parent, &l2_2711_lvl_intc_init);
  63 +}
  64 +
  65  IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
  66  IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
  67  IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
  68  IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
  69  IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
  70 +IRQCHIP_MATCH("brcm,bcm2711-l2-intc", brcmstb_l2_2711_lvl_intc_of_init)
  71  IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
  72  MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
  73  MODULE_LICENSE("GPL v2");