git.openwrt.org Git - openwrt/staging/adrian.git/blob

   1 From 4b777f389e22abb364e398f45673e54bcda9cc55 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.org>
   3 Date: Fri, 12 Jul 2019 11:41:25 +0100
   4 Subject: [PATCH] pcie-brcmstb: Bounce buffer support is for BCM2711B0
   5
   6 Add a new compatible string to identify BCM2711B0, as later revisions
   7 don't require the bounce buffer support.
   8
   9 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
  10 ---
  11  drivers/pci/controller/pcie-brcmstb.c | 31 +++++++++++++++++++++++----
  12  1 file changed, 27 insertions(+), 4 deletions(-)
  13
  14 --- a/drivers/pci/controller/pcie-brcmstb.c
  15 +++ b/drivers/pci/controller/pcie-brcmstb.c
  16 @@ -206,6 +206,8 @@ enum pcie_type {
  17         BCM7435,
  18         GENERIC,
  19         BCM7278,
  20 +       BCM2711B0,
  21 +       BCM2711,
  22  };
  23
  24  struct brcm_window {
  25 @@ -302,6 +304,20 @@ static const int pcie_offsets[] = {
  26         [EXT_CFG_DATA]   = 0x8000,
  27  };
  28
  29 +static const struct pcie_cfg_data bcm2711b0_cfg = {
  30 +       .reg_field_info = pcie_reg_field_info,
  31 +       .offsets        = pcie_offsets,
  32 +       .max_burst_size = BURST_SIZE_128,
  33 +       .type           = BCM2711B0,
  34 +};
  35 +
  36 +static const struct pcie_cfg_data bcm2711_cfg = {
  37 +       .reg_field_info = pcie_reg_field_info,
  38 +       .offsets        = pcie_offsets,
  39 +       .max_burst_size = BURST_SIZE_128,
  40 +       .type           = BCM2711,
  41 +};
  42 +
  43  static const struct pcie_cfg_data bcm7435_cfg = {
  44         .reg_field_info = pcie_reg_field_info,
  45         .offsets        = pcie_offsets,
  46 @@ -312,7 +328,7 @@ static const struct pcie_cfg_data bcm743
  47  static const struct pcie_cfg_data generic_cfg = {
  48         .reg_field_info = pcie_reg_field_info,
  49         .offsets        = pcie_offsets,
  50 -       .max_burst_size = BURST_SIZE_128, // before BURST_SIZE_512
  51 +       .max_burst_size = BURST_SIZE_512,
  52         .type           = GENERIC,
  53  };
  54
  55 @@ -380,7 +396,7 @@ static unsigned int bounce_buffer = 32*1
  56  module_param(bounce_buffer, uint, 0644);
  57  MODULE_PARM_DESC(bounce_buffer, "Size of bounce buffer");
  58
  59 -static unsigned int bounce_threshold = 0xc0000000;
  60 +static unsigned int bounce_threshold;
  61  module_param(bounce_threshold, uint, 0644);
  62  MODULE_PARM_DESC(bounce_threshold, "Bounce threshold");
  63
  64 @@ -1681,6 +1697,8 @@ static int brcm_pcie_remove(struct platf
  65  }
  66
  67  static const struct of_device_id brcm_pcie_match[] = {
  68 +       { .compatible = "brcm,bcm2711b0-pcie", .data = &bcm2711b0_cfg },
  69 +       { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
  70         { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
  71         { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
  72         { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
  73 @@ -1736,8 +1754,13 @@ static int brcm_pcie_probe(struct platfo
  74         if (IS_ERR(base))
  75                 return PTR_ERR(base);
  76
  77 -       /* To Do: Add hardware check if this ever gets fixed */
  78 -       if (max_pfn > (bounce_threshold/PAGE_SIZE)) {
  79 +       if (!bounce_threshold) {
  80 +               /* PCIe on BCM2711B0 can only address 3GB */
  81 +               if (pcie->type == BCM2711B0 || pcie->type == GENERIC)
  82 +                       bounce_threshold = 0xc0000000;
  83 +       }
  84 +
  85 +       if (bounce_threshold && (max_pfn > (bounce_threshold/PAGE_SIZE))) {
  86                 int ret;
  87                 ret = brcm_pcie_bounce_init(&pdev->dev, bounce_buffer,
  88                                             (dma_addr_t)bounce_threshold);