06d87ba5e0a633493c2f9394d6a302b09295f9d9
[openwrt/staging/thess.git] /
1
2 IMPORTANT NOTE
3 ==============
4
5 The content of this patch has been adapted for Linux 4.19
6
7 Changes were made in Linux 5.x to add the bad-block limit
8 to the metadata available to the driver, adding a parameter
9
10 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
11 ^- New bad-block limit
12
13 This patch omits that parameter from the upstream patch
14 for compatibility with the Linux 4.19 driver.
15
16 =====
17
18 From 049df13c4e63884fe6634db5568e08f65922256e Mon Sep 17 00:00:00 2001
19 From: Jeff Kletsky <git-commits@allycomm.com>
20 Date: Wed, 22 May 2019 15:05:55 -0700
21 Subject: [PATCH 3/3] mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG
22
23 The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
24 and, while it has the same logical layout as the E-series devices,
25 it differs in the SPI interfacing in significant ways.
26
27 This support is contingent on previous commits to:
28
29 * Add support for two-byte device IDs
30 * Define macros for page-read ops with three-byte addresses
31
32 http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
33
34 Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
35 Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
36 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
37 ---
38 drivers/mtd/nand/spi/gigadevice.c | 79 +++++++++++++++++++++++++------
39 1 file changed, 64 insertions(+), 15 deletions(-)
40
41 --- a/drivers/mtd/nand/spi/gigadevice.c
42 +++ b/drivers/mtd/nand/spi/gigadevice.c
43 @@ -9,11 +9,17 @@
44 #include <linux/mtd/spinand.h>
45
46 #define SPINAND_MFR_GIGADEVICE 0xC8
47 +
48 #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
49 #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
50
51 #define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
52
53 +#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
54 +#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
55 +#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4)
56 +#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
57 +
58 static SPINAND_OP_VARIANTS(read_cache_variants,
59 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
60 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
61 @@ -22,6 +28,14 @@ static SPINAND_OP_VARIANTS(read_cache_va
62 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
63 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
64
65 +static SPINAND_OP_VARIANTS(read_cache_variants_f,
66 + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
67 + SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
68 + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
69 + SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
70 + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
71 + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
72 +
73 static SPINAND_OP_VARIANTS(write_cache_variants,
74 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
75 SPINAND_PROG_LOAD(true, 0, NULL, 0));
76 @@ -59,6 +73,11 @@ static int gd5fxgq4xa_ooblayout_free(str
77 return 0;
78 }
79
80 +static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
81 + .ecc = gd5fxgq4xa_ooblayout_ecc,
82 + .free = gd5fxgq4xa_ooblayout_free,
83 +};
84 +
85 static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
86 u8 status)
87 {
88 @@ -83,7 +102,7 @@ static int gd5fxgq4xa_ecc_get_status(str
89 return -EINVAL;
90 }
91
92 -static int gd5fxgq4uexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
93 +static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
94 struct mtd_oob_region *region)
95 {
96 if (section)
97 @@ -95,7 +114,7 @@ static int gd5fxgq4uexxg_ooblayout_ecc(s
98 return 0;
99 }
100
101 -static int gd5fxgq4uexxg_ooblayout_free(struct mtd_info *mtd, int section,
102 +static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
103 struct mtd_oob_region *region)
104 {
105 if (section)
106 @@ -108,6 +127,11 @@ static int gd5fxgq4uexxg_ooblayout_free(
107 return 0;
108 }
109
110 +static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
111 + .ecc = gd5fxgq4_variant2_ooblayout_ecc,
112 + .free = gd5fxgq4_variant2_ooblayout_free,
113 +};
114 +
115 static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
116 u8 status)
117 {
118 @@ -150,15 +174,25 @@ static int gd5fxgq4uexxg_ecc_get_status(
119 return -EINVAL;
120 }
121
122 -static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
123 - .ecc = gd5fxgq4xa_ooblayout_ecc,
124 - .free = gd5fxgq4xa_ooblayout_free,
125 -};
126 +static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
127 + u8 status)
128 +{
129 + switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
130 + case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
131 + return 0;
132
133 -static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = {
134 - .ecc = gd5fxgq4uexxg_ooblayout_ecc,
135 - .free = gd5fxgq4uexxg_ooblayout_free,
136 -};
137 + case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
138 + return 3;
139 +
140 + case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
141 + return -EBADMSG;
142 +
143 + default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
144 + return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
145 + }
146 +
147 + return -EINVAL;
148 +}
149
150 static const struct spinand_info gigadevice_spinand_table[] = {
151 SPINAND_INFO("GD5F1GQ4xA", 0xF1,
152 @@ -195,25 +229,40 @@ static const struct spinand_info gigadev
153 &write_cache_variants,
154 &update_cache_variants),
155 0,
156 - SPINAND_ECCINFO(&gd5fxgq4uexxg_ooblayout,
157 + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
158 gd5fxgq4uexxg_ecc_get_status)),
159 + SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
160 + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
161 + NAND_ECCREQ(8, 512),
162 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
163 + &write_cache_variants,
164 + &update_cache_variants),
165 + 0,
166 + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
167 + gd5fxgq4ufxxg_ecc_get_status)),
168 };
169
170 static int gigadevice_spinand_detect(struct spinand_device *spinand)
171 {
172 u8 *id = spinand->id.data;
173 + u16 did;
174 int ret;
175
176 /*
177 - * For GD NANDs, There is an address byte needed to shift in before IDs
178 - * are read out, so the first byte in raw_id is dummy.
179 + * Earlier GDF5-series devices (A,E) return [0][MID][DID]
180 + * Later (F) devices return [MID][DID1][DID2]
181 */
182 - if (id[1] != SPINAND_MFR_GIGADEVICE)
183 +
184 + if (id[0] == SPINAND_MFR_GIGADEVICE)
185 + did = (id[1] << 8) + id[2];
186 + else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE)
187 + did = id[2];
188 + else
189 return 0;
190
191 ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
192 ARRAY_SIZE(gigadevice_spinand_table),
193 - id[2]);
194 + did);
195 if (ret)
196 return ret;
197