git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 31 Aug 2022 19:04:19 +0800
   4 Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all
   5  SoCs
   6
   7 Using a single soc id to control different initialization and TX/RX flow
   8 for all SoCs is not extensible if more hardware variations are added in
   9 the future.
  10
  11 This patch introduces a struct to replace the original mtk_soc to allow
  12 the driver be able handle newer hardwares.
  13
  14 Reviewed-by: Simon Glass <sjg@chromium.org>
  15 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  16 ---
  17  drivers/net/mtk_eth.c | 56 ++++++++++++++++++++++++++++++-------------
  18  drivers/net/mtk_eth.h | 25 ++++++++++++++++++-
  19  2 files changed, 64 insertions(+), 17 deletions(-)
  20
  21 --- a/drivers/net/mtk_eth.c
  22 +++ b/drivers/net/mtk_eth.c
  23 @@ -142,11 +142,15 @@ enum mtk_switch {
  24         SW_MT7531
  25  };
  26
  27 -enum mtk_soc {
  28 -       SOC_MT7623,
  29 -       SOC_MT7629,
  30 -       SOC_MT7622,
  31 -       SOC_MT7621
  32 +/* struct mtk_soc_data -       This is the structure holding all differences
  33 + *                             among various plaforms
  34 + * @caps                       Flags shown the extra capability for the SoC
  35 + * @ana_rgc3:                  The offset for register ANA_RGC3 related to
  36 + *                             sgmiisys syscon
  37 + */
  38 +struct mtk_soc_data {
  39 +       u32 caps;
  40 +       u32 ana_rgc3;
  41  };
  42
  43  struct mtk_eth_priv {
  44 @@ -171,7 +175,7 @@ struct mtk_eth_priv {
  45         int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
  46                          u16 val);
  47
  48 -       enum mtk_soc soc;
  49 +       const struct mtk_soc_data *soc;
  50         int gmac_id;
  51         int force_mode;
  52         int speed;
  53 @@ -679,7 +683,7 @@ static int mt7530_setup(struct mtk_eth_p
  54         u32 val, txdrv;
  55         int i;
  56
  57 -       if (priv->soc != SOC_MT7621) {
  58 +       if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
  59                 /* Select 250MHz clk for RGMII mode */
  60                 mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
  61                                ETHSYS_TRGMII_CLK_SEL362_5, 0);
  62 @@ -1108,9 +1112,8 @@ static int mtk_phy_probe(struct udevice
  63  static void mtk_sgmii_init(struct mtk_eth_priv *priv)
  64  {
  65         /* Set SGMII GEN2 speed(2.5G) */
  66 -       clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ?
  67 -                       SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2),
  68 -                       SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
  69 +       setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
  70 +                    SGMSYS_SPEED_2500);
  71
  72         /* Disable SGMII AN */
  73         clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
  74 @@ -1182,7 +1185,8 @@ static void mtk_mac_init(struct mtk_eth_
  75                 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
  76         }
  77
  78 -       if (priv->soc == SOC_MT7623) {
  79 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) &&
  80 +           !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
  81                 /* Lower Tx Driving for TRGMII path */
  82                 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
  83                         mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
  84 @@ -1431,7 +1435,11 @@ static int mtk_eth_of_to_plat(struct ude
  85         ofnode subnode;
  86         int ret;
  87
  88 -       priv->soc = dev_get_driver_data(dev);
  89 +       priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev);
  90 +       if (!priv->soc) {
  91 +               dev_err(dev, "missing soc compatible data\n");
  92 +               return -EINVAL;
  93 +       }
  94
  95         pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
  96
  97 @@ -1544,11 +1552,27 @@ static int mtk_eth_of_to_plat(struct ude
  98         return 0;
  99  }
 100
 101 +static const struct mtk_soc_data mt7629_data = {
 102 +       .ana_rgc3 = 0x128,
 103 +};
 104 +
 105 +static const struct mtk_soc_data mt7623_data = {
 106 +       .caps = MT7623_CAPS,
 107 +};
 108 +
 109 +static const struct mtk_soc_data mt7622_data = {
 110 +       .ana_rgc3 = 0x2028,
 111 +};
 112 +
 113 +static const struct mtk_soc_data mt7621_data = {
 114 +       .caps = MT7621_CAPS,
 115 +};
 116 +
 117  static const struct udevice_id mtk_eth_ids[] = {
 118 -       { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
 119 -       { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
 120 -       { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
 121 -       { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 },
 122 +       { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
 123 +       { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
 124 +       { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
 125 +       { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data },
 126         {}
 127  };
 128
 129 --- a/drivers/net/mtk_eth.h
 130 +++ b/drivers/net/mtk_eth.h
 131 @@ -9,8 +9,31 @@
 132  #ifndef _MTK_ETH_H_
 133  #define _MTK_ETH_H_
 134
 135 -/* Frame Engine Register Bases */
 136  #include <linux/bitops.h>
 137 +
 138 +enum mkt_eth_capabilities {
 139 +       MTK_TRGMII_BIT,
 140 +       MTK_TRGMII_MT7621_CLK_BIT,
 141 +
 142 +       /* PATH BITS */
 143 +       MTK_ETH_PATH_GMAC1_TRGMII_BIT,
 144 +};
 145 +
 146 +#define MTK_TRGMII                     BIT(MTK_TRGMII_BIT)
 147 +#define MTK_TRGMII_MT7621_CLK          BIT(MTK_TRGMII_MT7621_CLK_BIT)
 148 +
 149 +/* Supported path present on SoCs */
 150 +#define MTK_ETH_PATH_GMAC1_TRGMII      BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 151 +
 152 +#define MTK_GMAC1_TRGMII       (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
 153 +
 154 +#define MTK_HAS_CAPS(caps, _x)         (((caps) & (_x)) == (_x))
 155 +
 156 +#define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
 157 +
 158 +#define MT7623_CAPS  (MTK_GMAC1_TRGMII)
 159 +
 160 +/* Frame Engine Register Bases */
 161  #define PDMA_BASE                      0x0800
 162  #define GDMA1_BASE                     0x0500
 163  #define GDMA2_BASE                     0x1500