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1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
26
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31
32 #include "amdgpu_sync.h"
33 #include "amdgpu_ring.h"
34
35 struct amdgpu_bo_va;
36 struct amdgpu_job;
37 struct amdgpu_bo_list_entry;
38
39 /*
40 * GPUVM handling
41 */
42
43 /* maximum number of VMIDs */
44 #define AMDGPU_NUM_VM 16
45
46 /* Maximum number of PTEs the hardware can write with one command */
47 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
48
49 /* number of entries in page table */
50 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
51
52 /* PTBs (Page Table Blocks) need to be aligned to 32K */
53 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
54
55 #define AMDGPU_PTE_VALID (1ULL << 0)
56 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
57 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
58
59 /* VI only */
60 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
61
62 #define AMDGPU_PTE_READABLE (1ULL << 5)
63 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
64
65 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
66
67 /* TILED for VEGA10, reserved for older ASICs */
68 #define AMDGPU_PTE_PRT (1ULL << 51)
69
70 /* PDE is handled as PTE for VEGA10 */
71 #define AMDGPU_PDE_PTE (1ULL << 54)
72
73 /* VEGA10 only */
74 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
75 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
76
77 /* For Raven */
78 #define AMDGPU_MTYPE_CC 2
79
80 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
81 | AMDGPU_PTE_SNOOPED \
82 | AMDGPU_PTE_EXECUTABLE \
83 | AMDGPU_PTE_READABLE \
84 | AMDGPU_PTE_WRITEABLE \
85 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
86
87 /* How to programm VM fault handling */
88 #define AMDGPU_VM_FAULT_STOP_NEVER 0
89 #define AMDGPU_VM_FAULT_STOP_FIRST 1
90 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
91
92 /* max number of VMHUB */
93 #define AMDGPU_MAX_VMHUBS 2
94 #define AMDGPU_GFXHUB 0
95 #define AMDGPU_MMHUB 1
96
97 /* hardcode that limit for now */
98 #define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
99
100 /* VA hole for 48bit addresses on Vega10 */
101 #define AMDGPU_VA_HOLE_START 0x0000800000000000ULL
102 #define AMDGPU_VA_HOLE_END 0xffff800000000000ULL
103
104 /*
105 * Hardware is programmed as if the hole doesn't exists with start and end
106 * address values.
107 *
108 * This mask is used to remove the upper 16bits of the VA and so come up with
109 * the linear addr value.
110 */
111 #define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL
112
113 /* max vmids dedicated for process */
114 #define AMDGPU_VM_MAX_RESERVED_VMID 1
115
116 #define AMDGPU_VM_CONTEXT_GFX 0
117 #define AMDGPU_VM_CONTEXT_COMPUTE 1
118
119 /* See vm_update_mode */
120 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
121 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
122
123 /* VMPT level enumerate, and the hiberachy is:
124 * PDB2->PDB1->PDB0->PTB
125 */
126 enum amdgpu_vm_level {
127 AMDGPU_VM_PDB2,
128 AMDGPU_VM_PDB1,
129 AMDGPU_VM_PDB0,
130 AMDGPU_VM_PTB
131 };
132
133 /* base structure for tracking BO usage in a VM */
134 struct amdgpu_vm_bo_base {
135 /* constant after initialization */
136 struct amdgpu_vm *vm;
137 struct amdgpu_bo *bo;
138
139 /* protected by bo being reserved */
140 struct list_head bo_list;
141
142 /* protected by spinlock */
143 struct list_head vm_status;
144
145 /* protected by the BO being reserved */
146 bool moved;
147 };
148
149 struct amdgpu_vm_pt {
150 struct amdgpu_vm_bo_base base;
151 bool huge;
152
153 /* array of page tables, one for each directory entry */
154 struct amdgpu_vm_pt *entries;
155 };
156
157 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
158 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
159 #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
160
161 struct amdgpu_vm {
162 /* tree of virtual addresses mapped */
163 struct rb_root_cached va;
164
165 /* protecting invalidated */
166 spinlock_t status_lock;
167
168 /* BOs who needs a validation */
169 struct list_head evicted;
170
171 /* PT BOs which relocated and their parent need an update */
172 struct list_head relocated;
173
174 /* BOs moved, but not yet updated in the PT */
175 struct list_head moved;
176
177 /* BO mappings freed, but not yet updated in the PT */
178 struct list_head freed;
179
180 /* contains the page directory */
181 struct amdgpu_vm_pt root;
182 struct dma_fence *last_update;
183
184 /* protecting freed */
185 spinlock_t freed_lock;
186
187 /* Scheduler entity for page table updates */
188 struct drm_sched_entity entity;
189
190 /* client id and PASID (TODO: replace client_id with PASID) */
191 u64 client_id;
192 unsigned int pasid;
193 /* dedicated to vm */
194 struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS];
195
196 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
197 bool use_cpu_for_update;
198
199 /* Flag to indicate ATS support from PTE for GFX9 */
200 bool pte_support_ats;
201
202 /* Up to 128 pending retry page faults */
203 DECLARE_KFIFO(faults, u64, 128);
204
205 /* Limit non-retry fault storms */
206 unsigned int fault_credit;
207 };
208
209 struct amdgpu_vm_id {
210 struct list_head list;
211 struct amdgpu_sync active;
212 struct dma_fence *last_flush;
213 atomic64_t owner;
214
215 uint64_t pd_gpu_addr;
216 /* last flushed PD/PT update */
217 struct dma_fence *flushed_updates;
218
219 uint32_t current_gpu_reset_count;
220
221 uint32_t gds_base;
222 uint32_t gds_size;
223 uint32_t gws_base;
224 uint32_t gws_size;
225 uint32_t oa_base;
226 uint32_t oa_size;
227 };
228
229 struct amdgpu_vm_id_manager {
230 struct mutex lock;
231 unsigned num_ids;
232 struct list_head ids_lru;
233 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
234 atomic_t reserved_vmid_num;
235 };
236
237 struct amdgpu_vm_manager {
238 /* Handling of VMIDs */
239 struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS];
240
241 /* Handling of VM fences */
242 u64 fence_context;
243 unsigned seqno[AMDGPU_MAX_RINGS];
244
245 uint64_t max_pfn;
246 uint32_t num_level;
247 uint32_t block_size;
248 uint32_t fragment_size;
249 enum amdgpu_vm_level root_level;
250 /* vram base address for page table entry */
251 u64 vram_base_offset;
252 /* vm pte handling */
253 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
254 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
255 unsigned vm_pte_num_rings;
256 atomic_t vm_pte_next_ring;
257 /* client id counter */
258 atomic64_t client_counter;
259
260 /* partial resident texture handling */
261 spinlock_t prt_lock;
262 atomic_t num_prt_users;
263
264 /* controls how VM page tables are updated for Graphics and Compute.
265 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
266 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
267 */
268 int vm_update_mode;
269
270 /* PASID to VM mapping, will be used in interrupt context to
271 * look up VM of a page fault
272 */
273 struct idr pasid_idr;
274 spinlock_t pasid_lock;
275 };
276
277 int amdgpu_vm_alloc_pasid(unsigned int bits);
278 void amdgpu_vm_free_pasid(unsigned int pasid);
279 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
280 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
281 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
282 int vm_context, unsigned int pasid);
283 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
284 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
285 unsigned int pasid);
286 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
287 struct list_head *validated,
288 struct amdgpu_bo_list_entry *entry);
289 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
290 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
291 int (*callback)(void *p, struct amdgpu_bo *bo),
292 void *param);
293 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
294 struct amdgpu_vm *vm,
295 uint64_t saddr, uint64_t size);
296 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
297 struct amdgpu_sync *sync, struct dma_fence *fence,
298 struct amdgpu_job *job);
299 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
300 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
301 unsigned vmid);
302 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
303 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
304 struct amdgpu_vm *vm);
305 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
306 struct amdgpu_vm *vm,
307 struct dma_fence **fence);
308 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
309 struct amdgpu_vm *vm);
310 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
311 struct amdgpu_bo_va *bo_va,
312 bool clear);
313 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
314 struct amdgpu_bo *bo, bool evicted);
315 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
316 struct amdgpu_bo *bo);
317 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
318 struct amdgpu_vm *vm,
319 struct amdgpu_bo *bo);
320 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
321 struct amdgpu_bo_va *bo_va,
322 uint64_t addr, uint64_t offset,
323 uint64_t size, uint64_t flags);
324 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
325 struct amdgpu_bo_va *bo_va,
326 uint64_t addr, uint64_t offset,
327 uint64_t size, uint64_t flags);
328 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
329 struct amdgpu_bo_va *bo_va,
330 uint64_t addr);
331 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
332 struct amdgpu_vm *vm,
333 uint64_t saddr, uint64_t size);
334 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
335 uint64_t addr);
336 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
337 struct amdgpu_bo_va *bo_va);
338 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
339 uint32_t fragment_size_default, unsigned max_level,
340 unsigned max_bits);
341 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
342 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
343 struct amdgpu_job *job);
344 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
345
346 #endif
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