git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From a1126887f068def0bc11f5260e55e25b9c03e3ea Mon Sep 17 00:00:00 2001
   2 From: Marc Kleine-Budde <mkl@pengutronix.de>
   3 Date: Fri, 1 Mar 2019 09:18:54 +0100
   4 Subject: [PATCH] can: flexcan: rename struct
   5  flexcan_priv::reg_imask{1,2}_default to rx_mask{1,2}
   6
   7 The flexcan IP core has up to 64 mailboxes, each one has a corresponding
   8 interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
   9 imask1 or imask2 registers.
  10
  11 In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
  12 non RX interrupt sources and uses the precomputed values
  13 reg_imask1_default and reg_imask2_default of struct flexcan_priv for
  14 this.
  15
  16 However in the current driver the reg_imask{1,2}_default cannot be used
  17 directly to get the pending RX interrupts. The TX interrupt is part of
  18 these variables, so it needs to be masked out, too.
  19
  20 This is a preparation patch to clean up calculation of the pending RX
  21 interrupts, it only renames the variables from
  22
  23     reg_imask{1,2}_default
  24
  25 to
  26
  27     rx_mask{1,2}
  28
  29 To better reflect their meaning after the complete conversion. This
  30 change is done with the following sed command:
  31
  32     sed -i -e "s/reg_imask\(1\|2\)_default/rx_mask\1/" drivers/net/can/flexcan.c
  33
  34 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
  35 ---
  36  drivers/net/can/flexcan.c | 22 +++++++++++-----------
  37  1 file changed, 11 insertions(+), 11 deletions(-)
  38
  39 --- a/drivers/net/can/flexcan.c
  40 +++ b/drivers/net/can/flexcan.c
  41 @@ -278,8 +278,8 @@ struct flexcan_priv {
  42         u8 clk_src;     /* clock source of CAN Protocol Engine */
  43
  44         u32 reg_ctrl_default;
  45 -       u32 reg_imask1_default;
  46 -       u32 reg_imask2_default;
  47 +       u32 rx_mask1;
  48 +       u32 rx_mask2;
  49
  50         struct clk *clk_ipg;
  51         struct clk *clk_per;
  52 @@ -879,9 +879,9 @@ static inline u64 flexcan_read_reg_iflag
  53         struct flexcan_regs __iomem *regs = priv->regs;
  54         u32 iflag1, iflag2;
  55
  56 -       iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
  57 +       iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2 &
  58                 ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
  59 -       iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
  60 +       iflag1 = priv->read(&regs->iflag1) & priv->rx_mask1;
  61
  62         return (u64)iflag2 << 32 | iflag1;
  63  }
  64 @@ -1228,8 +1228,8 @@ static int flexcan_chip_start(struct net
  65         /* enable interrupts atomically */
  66         disable_irq(dev->irq);
  67         priv->write(priv->reg_ctrl_default, &regs->ctrl);
  68 -       priv->write(priv->reg_imask1_default, &regs->imask1);
  69 -       priv->write(priv->reg_imask2_default, &regs->imask2);
  70 +       priv->write(priv->rx_mask1, &regs->imask1);
  71 +       priv->write(priv->rx_mask2, &regs->imask2);
  72         enable_irq(dev->irq);
  73
  74         /* print chip status */
  75 @@ -1298,8 +1298,8 @@ static int flexcan_open(struct net_devic
  76         priv->tx_mb_idx = priv->mb_count - 1;
  77         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
  78
  79 -       priv->reg_imask1_default = 0;
  80 -       priv->reg_imask2_default = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
  81 +       priv->rx_mask1 = 0;
  82 +       priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
  83
  84         priv->offload.mailbox_read = flexcan_mailbox_read;
  85
  86 @@ -1311,12 +1311,12 @@ static int flexcan_open(struct net_devic
  87
  88                 imask = GENMASK_ULL(priv->offload.mb_last,
  89                                     priv->offload.mb_first);
  90 -               priv->reg_imask1_default |= imask;
  91 -               priv->reg_imask2_default |= imask >> 32;
  92 +               priv->rx_mask1 |= imask;
  93 +               priv->rx_mask2 |= imask >> 32;
  94
  95                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
  96         } else {
  97 -               priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
  98 +               priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
  99                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
 100                 err = can_rx_offload_add_fifo(dev, &priv->offload,
 101                                               FLEXCAN_NAPI_WEIGHT);