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1 From 999db52750c062708532e1357ea3942cc619794f Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Wed, 18 Jan 2017 07:31:55 +1100
4 Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL
5 dividers.
6
7 Our core PLLs are intended to be configured once and left alone. With
8 the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
9 change PLLD just to get closer to the requested DSI clock, thus
10 changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
11 it, and breaking ethernet.
12
13 We *do* want PLLH to change so that PLLH_AUX can be exactly the value
14 we want, though. Thus, we need to have a per-divider policy of
15 whether to pass rate changes up.
16
17 Signed-off-by: Eric Anholt <eric@anholt.net>
18 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
19 (cherry picked from commit 55486091bd1e1c5ed28c43c0d6b3392468a9adb5)
20 ---
21 drivers/clk/bcm/clk-bcm2835.c | 42 ++++++++++++++++++++++++++++--------------
22 1 file changed, 28 insertions(+), 14 deletions(-)
23
24 --- a/drivers/clk/bcm/clk-bcm2835.c
25 +++ b/drivers/clk/bcm/clk-bcm2835.c
26 @@ -428,6 +428,7 @@ struct bcm2835_pll_divider_data {
27 u32 load_mask;
28 u32 hold_mask;
29 u32 fixed_divider;
30 + u32 flags;
31 };
32
33 struct bcm2835_clock_data {
34 @@ -1256,7 +1257,7 @@ bcm2835_register_pll_divider(struct bcm2
35 init.num_parents = 1;
36 init.name = divider_name;
37 init.ops = &bcm2835_pll_divider_clk_ops;
38 - init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
39 + init.flags = data->flags | CLK_IGNORE_UNUSED;
40
41 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
42 if (!divider)
43 @@ -1479,7 +1480,8 @@ static const struct bcm2835_clk_desc clk
44 .a2w_reg = A2W_PLLA_CORE,
45 .load_mask = CM_PLLA_LOADCORE,
46 .hold_mask = CM_PLLA_HOLDCORE,
47 - .fixed_divider = 1),
48 + .fixed_divider = 1,
49 + .flags = CLK_SET_RATE_PARENT),
50 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
51 .name = "plla_per",
52 .source_pll = "plla",
53 @@ -1487,7 +1489,8 @@ static const struct bcm2835_clk_desc clk
54 .a2w_reg = A2W_PLLA_PER,
55 .load_mask = CM_PLLA_LOADPER,
56 .hold_mask = CM_PLLA_HOLDPER,
57 - .fixed_divider = 1),
58 + .fixed_divider = 1,
59 + .flags = CLK_SET_RATE_PARENT),
60 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
61 .name = "plla_dsi0",
62 .source_pll = "plla",
63 @@ -1503,7 +1506,8 @@ static const struct bcm2835_clk_desc clk
64 .a2w_reg = A2W_PLLA_CCP2,
65 .load_mask = CM_PLLA_LOADCCP2,
66 .hold_mask = CM_PLLA_HOLDCCP2,
67 - .fixed_divider = 1),
68 + .fixed_divider = 1,
69 + .flags = CLK_SET_RATE_PARENT),
70
71 /* PLLB is used for the ARM's clock. */
72 [BCM2835_PLLB] = REGISTER_PLL(
73 @@ -1527,7 +1531,8 @@ static const struct bcm2835_clk_desc clk
74 .a2w_reg = A2W_PLLB_ARM,
75 .load_mask = CM_PLLB_LOADARM,
76 .hold_mask = CM_PLLB_HOLDARM,
77 - .fixed_divider = 1),
78 + .fixed_divider = 1,
79 + .flags = CLK_SET_RATE_PARENT),
80
81 /*
82 * PLLC is the core PLL, used to drive the core VPU clock.
83 @@ -1556,7 +1561,8 @@ static const struct bcm2835_clk_desc clk
84 .a2w_reg = A2W_PLLC_CORE0,
85 .load_mask = CM_PLLC_LOADCORE0,
86 .hold_mask = CM_PLLC_HOLDCORE0,
87 - .fixed_divider = 1),
88 + .fixed_divider = 1,
89 + .flags = CLK_SET_RATE_PARENT),
90 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
91 .name = "pllc_core1",
92 .source_pll = "pllc",
93 @@ -1564,7 +1570,8 @@ static const struct bcm2835_clk_desc clk
94 .a2w_reg = A2W_PLLC_CORE1,
95 .load_mask = CM_PLLC_LOADCORE1,
96 .hold_mask = CM_PLLC_HOLDCORE1,
97 - .fixed_divider = 1),
98 + .fixed_divider = 1,
99 + .flags = CLK_SET_RATE_PARENT),
100 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
101 .name = "pllc_core2",
102 .source_pll = "pllc",
103 @@ -1572,7 +1579,8 @@ static const struct bcm2835_clk_desc clk
104 .a2w_reg = A2W_PLLC_CORE2,
105 .load_mask = CM_PLLC_LOADCORE2,
106 .hold_mask = CM_PLLC_HOLDCORE2,
107 - .fixed_divider = 1),
108 + .fixed_divider = 1,
109 + .flags = CLK_SET_RATE_PARENT),
110 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
111 .name = "pllc_per",
112 .source_pll = "pllc",
113 @@ -1580,7 +1588,8 @@ static const struct bcm2835_clk_desc clk
114 .a2w_reg = A2W_PLLC_PER,
115 .load_mask = CM_PLLC_LOADPER,
116 .hold_mask = CM_PLLC_HOLDPER,
117 - .fixed_divider = 1),
118 + .fixed_divider = 1,
119 + .flags = CLK_SET_RATE_PARENT),
120
121 /*
122 * PLLD is the display PLL, used to drive DSI display panels.
123 @@ -1609,7 +1618,8 @@ static const struct bcm2835_clk_desc clk
124 .a2w_reg = A2W_PLLD_CORE,
125 .load_mask = CM_PLLD_LOADCORE,
126 .hold_mask = CM_PLLD_HOLDCORE,
127 - .fixed_divider = 1),
128 + .fixed_divider = 1,
129 + .flags = CLK_SET_RATE_PARENT),
130 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
131 .name = "plld_per",
132 .source_pll = "plld",
133 @@ -1617,7 +1627,8 @@ static const struct bcm2835_clk_desc clk
134 .a2w_reg = A2W_PLLD_PER,
135 .load_mask = CM_PLLD_LOADPER,
136 .hold_mask = CM_PLLD_HOLDPER,
137 - .fixed_divider = 1),
138 + .fixed_divider = 1,
139 + .flags = CLK_SET_RATE_PARENT),
140 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
141 .name = "plld_dsi0",
142 .source_pll = "plld",
143 @@ -1662,7 +1673,8 @@ static const struct bcm2835_clk_desc clk
144 .a2w_reg = A2W_PLLH_RCAL,
145 .load_mask = CM_PLLH_LOADRCAL,
146 .hold_mask = 0,
147 - .fixed_divider = 10),
148 + .fixed_divider = 10,
149 + .flags = CLK_SET_RATE_PARENT),
150 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
151 .name = "pllh_aux",
152 .source_pll = "pllh",
153 @@ -1670,7 +1682,8 @@ static const struct bcm2835_clk_desc clk
154 .a2w_reg = A2W_PLLH_AUX,
155 .load_mask = CM_PLLH_LOADAUX,
156 .hold_mask = 0,
157 - .fixed_divider = 1),
158 + .fixed_divider = 1,
159 + .flags = CLK_SET_RATE_PARENT),
160 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
161 .name = "pllh_pix",
162 .source_pll = "pllh",
163 @@ -1678,7 +1691,8 @@ static const struct bcm2835_clk_desc clk
164 .a2w_reg = A2W_PLLH_PIX,
165 .load_mask = CM_PLLH_LOADPIX,
166 .hold_mask = 0,
167 - .fixed_divider = 10),
168 + .fixed_divider = 10,
169 + .flags = CLK_SET_RATE_PARENT),
170
171 /* the clocks */
172
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