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   1 From 01ffdd37dcd3c9e526ac9135bfd289beb45f84a0 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Wed, 10 Feb 2016 16:17:29 -0800
   4 Subject: [PATCH] drm/vc4: Add support for feeding DSI encoders from the pixel
   5  valve.
   6
   7 We have to set a different pixel format, which tells the hardware to
   8 use the pix_width field that's fed in sideband from the DSI encoder to
   9 divide the "pixel" clock.
  10
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_crtc.c | 33 +++++++++++++++++++--------------
  14  drivers/gpu/drm/vc4/vc4_regs.h |  2 ++
  15  2 files changed, 21 insertions(+), 14 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  19 @@ -352,38 +352,40 @@ static u32 vc4_get_fifo_full_level(u32 f
  20  }
  21
  22  /*
  23 - * Returns the clock select bit for the connector attached to the
  24 - * CRTC.
  25 + * Returns the encoder attached to the CRTC.
  26 + *
  27 + * VC4 can only scan out to one encoder at a time, while the DRM core
  28 + * allows drivers to push pixels to more than one encoder from the
  29 + * same CRTC.
  30   */
  31 -static int vc4_get_clock_select(struct drm_crtc *crtc)
  32 +static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
  33  {
  34         struct drm_connector *connector;
  35
  36         drm_for_each_connector(connector, crtc->dev) {
  37                 if (connector->state->crtc == crtc) {
  38 -                       struct drm_encoder *encoder = connector->encoder;
  39 -                       struct vc4_encoder *vc4_encoder =
  40 -                               to_vc4_encoder(encoder);
  41 -
  42 -                       return vc4_encoder->clock_select;
  43 +                       return connector->encoder;
  44                 }
  45         }
  46
  47 -       return -1;
  48 +       return NULL;
  49  }
  50
  51  static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
  52  {
  53         struct drm_device *dev = crtc->dev;
  54         struct vc4_dev *vc4 = to_vc4_dev(dev);
  55 +       struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
  56 +       struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
  57         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  58         struct drm_crtc_state *state = crtc->state;
  59         struct drm_display_mode *mode = &state->adjusted_mode;
  60         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
  61         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
  62 -       u32 format = PV_CONTROL_FORMAT_24;
  63 +       bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
  64 +                      vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
  65 +       u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
  66         bool debug_dump_regs = false;
  67 -       int clock_select = vc4_get_clock_select(crtc);
  68
  69         if (debug_dump_regs) {
  70                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
  71 @@ -439,17 +441,19 @@ static void vc4_crtc_mode_set_nofb(struc
  72                  */
  73                 CRTC_WRITE(PV_V_CONTROL,
  74                            PV_VCONTROL_CONTINUOUS |
  75 +                          (is_dsi ? PV_VCONTROL_DSI : 0) |
  76                            PV_VCONTROL_INTERLACE |
  77                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
  78                                          PV_VCONTROL_ODD_DELAY));
  79                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
  80         } else {
  81 -               CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
  82 +               CRTC_WRITE(PV_V_CONTROL,
  83 +                          PV_VCONTROL_CONTINUOUS |
  84 +                          (is_dsi ? PV_VCONTROL_DSI : 0));
  85         }
  86
  87         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
  88
  89 -
  90         CRTC_WRITE(PV_CONTROL,
  91                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
  92                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
  93 @@ -458,7 +462,8 @@ static void vc4_crtc_mode_set_nofb(struc
  94                    PV_CONTROL_CLR_AT_START |
  95                    PV_CONTROL_TRIGGER_UNDERFLOW |
  96                    PV_CONTROL_WAIT_HSTART |
  97 -                  VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
  98 +                  VC4_SET_FIELD(vc4_encoder->clock_select,
  99 +                                PV_CONTROL_CLK_SELECT) |
 100                    PV_CONTROL_FIFO_CLR |
 101                    PV_CONTROL_EN);
 102
 103 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 104 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 105 @@ -190,6 +190,8 @@
 106  # define PV_VCONTROL_ODD_DELAY_SHIFT           6
 107  # define PV_VCONTROL_ODD_FIRST                 BIT(5)
 108  # define PV_VCONTROL_INTERLACE                 BIT(4)
 109 +# define PV_VCONTROL_DSI                       BIT(3)
 110 +# define PV_VCONTROL_COMMAND                   BIT(2)
 111  # define PV_VCONTROL_CONTINUOUS                        BIT(1)
 112  # define PV_VCONTROL_VIDEN                     BIT(0)
 113