17286a815e16385724f7337600898306f18365de
[openwrt/staging/chunkeey.git] /
1 From 3dc3a4c6ac9e8a0940a9974b8fe2da7641bfa3dd Mon Sep 17 00:00:00 2001
2 From: Alex Marginean <alexandru.marginean@nxp.com>
3 Date: Thu, 22 Aug 2019 12:47:12 +0300
4 Subject: [PATCH] arm64: dts: LS1028a-rdb: use Ethernet PHY interrupt
5
6 Use the PHY interrupt wired to GPIO pins as part of MDIO WA performance
7 impact mitigation.
8
9 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
10 ---
11 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 10 ++++++++++
12 1 file changed, 10 insertions(+)
13
14 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
15 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
16 @@ -202,6 +202,8 @@
17 #size-cells = <0>;
18 sgmii_phy0: ethernet-phy@2 {
19 reg = <0x2>;
20 + interrupt-parent = <&gpio1>;
21 + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
22 };
23 };
24 };
25 @@ -213,18 +215,26 @@
26 &enetc_mdio_pf3 {
27 qsgmii_phy1: ethernet-phy@4 {
28 reg = <0x10>;
29 + interrupt-parent = <&gpio1>;
30 + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
31 };
32
33 qsgmii_phy2: ethernet-phy@5 {
34 reg = <0x11>;
35 + interrupt-parent = <&gpio1>;
36 + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
37 };
38
39 qsgmii_phy3: ethernet-phy@6 {
40 reg = <0x12>;
41 + interrupt-parent = <&gpio1>;
42 + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
43 };
44
45 qsgmii_phy4: ethernet-phy@7 {
46 reg = <0x13>;
47 + interrupt-parent = <&gpio1>;
48 + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
49 };
50 };
51