git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 6e3a17190815c6aa4dc53c2cfe9125fb1154f187 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sun, 24 Mar 2013 19:26:27 +0100
   4 Subject: [PATCH] rt2x00: rt2800lib: add channel configuration function for
   5  RF3853
   6
   7 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   8 ---
   9  drivers/net/wireless/ralink/rt2x00/rt2800lib.c |  208 +++++++++++++++++++++++++++++++
  10  1 file changed, 208 insertions(+)
  11
  12 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  13 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  14 @@ -2716,6 +2716,211 @@ static void rt2800_config_channel_rf3053
  15         }
  16  }
  17
  18 +static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
  19 +                                        struct ieee80211_conf *conf,
  20 +                                        struct rf_channel *rf,
  21 +                                        struct channel_info *info)
  22 +{
  23 +       u8 rfcsr;
  24 +       u8 bbp;
  25 +       u8 pwr1, pwr2, pwr3;
  26 +
  27 +       const bool txbf_enabled = false; /* TODO */
  28 +
  29 +       /* TODO: add band selection */
  30 +
  31 +       if (rf->channel <= 14)
  32 +               rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
  33 +       else if (rf->channel < 132)
  34 +               rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
  35 +       else
  36 +               rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
  37 +
  38 +       rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  39 +       rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
  40 +
  41 +       if (rf->channel <= 14)
  42 +               rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
  43 +       else
  44 +               rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
  45 +
  46 +       if (rf->channel <= 14)
  47 +               rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
  48 +       else
  49 +               rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
  50 +
  51 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
  52 +
  53 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
  54 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  55 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  56 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
  57 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
  58 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  59 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  60 +       rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  61 +       rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
  62 +
  63 +       switch (rt2x00dev->default_ant.tx_chain_num) {
  64 +       case 3:
  65 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
  66 +               /* fallthrough */
  67 +       case 2:
  68 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  69 +               /* fallthrough */
  70 +       case 1:
  71 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  72 +               break;
  73 +       }
  74 +
  75 +       switch (rt2x00dev->default_ant.rx_chain_num) {
  76 +       case 3:
  77 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
  78 +               /* fallthrough */
  79 +       case 2:
  80 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  81 +               /* fallthrough */
  82 +       case 1:
  83 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  84 +               break;
  85 +       }
  86 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  87 +
  88 +       rt2800_freq_cal_mode1(rt2x00dev);
  89 +
  90 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
  91 +       if (!conf_is_ht40(conf))
  92 +               rfcsr &= ~(0x06);
  93 +       else
  94 +               rfcsr |= 0x06;
  95 +       rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  96 +
  97 +       if (rf->channel <= 14)
  98 +               rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
  99 +       else
 100 +               rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 101 +
 102 +       if (conf_is_ht40(conf))
 103 +               rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 104 +       else
 105 +               rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
 106 +
 107 +       if (rf->channel <= 14)
 108 +               rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
 109 +       else
 110 +               rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
 111 +
 112 +       /* loopback RF_BS */
 113 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
 114 +       if (rf->channel <= 14)
 115 +               rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
 116 +       else
 117 +               rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
 118 +       rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
 119 +
 120 +       if (rf->channel <= 14)
 121 +               rfcsr = 0x23;
 122 +       else if (rf->channel < 100)
 123 +               rfcsr = 0x36;
 124 +       else if (rf->channel < 132)
 125 +               rfcsr = 0x32;
 126 +       else
 127 +               rfcsr = 0x30;
 128 +
 129 +       if (txbf_enabled)
 130 +               rfcsr |= 0x40;
 131 +
 132 +       rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 133 +
 134 +       if (rf->channel <= 14)
 135 +               rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
 136 +       else
 137 +               rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
 138 +
 139 +       if (rf->channel <= 14)
 140 +               rfcsr = 0xbb;
 141 +       else if (rf->channel < 100)
 142 +               rfcsr = 0xeb;
 143 +       else if (rf->channel < 132)
 144 +               rfcsr = 0xb3;
 145 +       else
 146 +               rfcsr = 0x9b;
 147 +       rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
 148 +
 149 +       if (rf->channel <= 14)
 150 +               rfcsr = 0x8e;
 151 +       else
 152 +               rfcsr = 0x8a;
 153 +
 154 +       if (txbf_enabled)
 155 +               rfcsr |= 0x20;
 156 +
 157 +       rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 158 +
 159 +       rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
 160 +
 161 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
 162 +       if (rf->channel <= 14)
 163 +               rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
 164 +       else
 165 +               rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
 166 +
 167 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
 168 +       if (rf->channel <= 14)
 169 +               rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
 170 +       else
 171 +               rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
 172 +
 173 +       if (rf->channel <= 14) {
 174 +               pwr1 = info->default_power1 & 0x1f;
 175 +               pwr2 = info->default_power2 & 0x1f;
 176 +               pwr3 = info->default_power3 & 0x1f;
 177 +       } else {
 178 +               pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
 179 +                       (info->default_power1 & 0x7);
 180 +               pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
 181 +                       (info->default_power2 & 0x7);
 182 +               pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
 183 +                       (info->default_power3 & 0x7);
 184 +       }
 185 +
 186 +       rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
 187 +       rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
 188 +       rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
 189 +
 190 +       rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
 191 +                  rf->channel, pwr1, pwr2, pwr3);
 192 +
 193 +       bbp = (info->default_power1 >> 5) |
 194 +             ((info->default_power2 & 0xe0) >> 1);
 195 +       rt2800_bbp_write(rt2x00dev, 109, bbp);
 196 +
 197 +       bbp = rt2800_bbp_read(rt2x00dev, 110);
 198 +       bbp &= 0x0f;
 199 +       bbp |= (info->default_power3 & 0xe0) >> 1;
 200 +       rt2800_bbp_write(rt2x00dev, 110, bbp);
 201 +
 202 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
 203 +       if (rf->channel <= 14)
 204 +               rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
 205 +       else
 206 +               rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
 207 +
 208 +       /* Enable RF tuning */
 209 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
 210 +       rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 211 +       rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 212 +
 213 +       udelay(2000);
 214 +
 215 +       bbp = rt2800_bbp_read(rt2x00dev, 49);
 216 +       /* clear update flag */
 217 +       rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
 218 +       rt2800_bbp_write(rt2x00dev, 49, bbp);
 219 +
 220 +       /* TODO: add calibration for TxBF */
 221 +}
 222 +
 223  #define POWER_BOUND            0x27
 224  #define POWER_BOUND_5G         0x2b
 225
 226 @@ -3573,6 +3778,9 @@ static void rt2800_config_channel(struct
 227         case RF3322:
 228                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
 229                 break;
 230 +       case RF3853:
 231 +               rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
 232 +               break;
 233         case RF3070:
 234         case RF5350:
 235         case RF5360: