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1 From 65a4a80157bacde3cf86ce8cbc9a08f5f05ad9bb Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:21:34 +0800
4 Subject: [PATCH 01/25] mips: add asm/mipsmtregs.h for MIPS multi-threading
5
6 To be compatible with old u-boot used by lots of MT7621 devices, the u-boot
7 needs to boot-up MT7621's all cores, and all VPES of each core.
8
9 This patch adds asm/mipsmtregs.h from linux kernel which is need for
10 boot-up VPEs.
11
12 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
13 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
14 ---
15 arch/mips/include/asm/mipsmtregs.h | 142 +++++++++++++++++++++++++++++
16 1 file changed, 142 insertions(+)
17 create mode 100644 arch/mips/include/asm/mipsmtregs.h
18
19 diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
20 new file mode 100644
21 index 0000000000..ba82e2bd97
22 --- /dev/null
23 +++ b/arch/mips/include/asm/mipsmtregs.h
24 @@ -0,0 +1,142 @@
25 +/* SPDX-License-Identifier: GPL-2.0 */
26 +/*
27 + * MT regs definitions, follows on from mipsregs.h
28 + * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
29 + * Elizabeth Clarke et. al.
30 + *
31 + */
32 +#ifndef _ASM_MIPSMTREGS_H
33 +#define _ASM_MIPSMTREGS_H
34 +
35 +#include <asm/mipsregs.h>
36 +
37 +/*
38 + * Macros for use in assembly language code
39 + */
40 +
41 +#define CP0_MVPCONTROL $0, 1
42 +#define CP0_MVPCONF0 $0, 2
43 +#define CP0_MVPCONF1 $0, 3
44 +#define CP0_VPECONTROL $1, 1
45 +#define CP0_VPECONF0 $1, 2
46 +#define CP0_VPECONF1 $1, 3
47 +#define CP0_YQMASK $1, 4
48 +#define CP0_VPESCHEDULE $1, 5
49 +#define CP0_VPESCHEFBK $1, 6
50 +#define CP0_TCSTATUS $2, 1
51 +#define CP0_TCBIND $2, 2
52 +#define CP0_TCRESTART $2, 3
53 +#define CP0_TCHALT $2, 4
54 +#define CP0_TCCONTEXT $2, 5
55 +#define CP0_TCSCHEDULE $2, 6
56 +#define CP0_TCSCHEFBK $2, 7
57 +#define CP0_SRSCONF0 $6, 1
58 +#define CP0_SRSCONF1 $6, 2
59 +#define CP0_SRSCONF2 $6, 3
60 +#define CP0_SRSCONF3 $6, 4
61 +#define CP0_SRSCONF4 $6, 5
62 +
63 +/* MVPControl fields */
64 +#define MVPCONTROL_EVP (_ULCAST_(1))
65 +
66 +#define MVPCONTROL_VPC_SHIFT 1
67 +#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
68 +
69 +#define MVPCONTROL_STLB_SHIFT 2
70 +#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
71 +
72 +/* MVPConf0 fields */
73 +#define MVPCONF0_PTC_SHIFT 0
74 +#define MVPCONF0_PTC (_ULCAST_(0xff))
75 +#define MVPCONF0_PVPE_SHIFT 10
76 +#define MVPCONF0_PVPE (_ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
77 +#define MVPCONF0_TCA_SHIFT 15
78 +#define MVPCONF0_TCA (_ULCAST_(1) << MVPCONF0_TCA_SHIFT)
79 +#define MVPCONF0_PTLBE_SHIFT 16
80 +#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
81 +#define MVPCONF0_TLBS_SHIFT 29
82 +#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
83 +#define MVPCONF0_M_SHIFT 31
84 +#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
85 +
86 +/* config3 fields */
87 +#define CONFIG3_MT_SHIFT 2
88 +#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
89 +
90 +/* VPEControl fields (per VPE) */
91 +#define VPECONTROL_TARGTC (_ULCAST_(0xff))
92 +
93 +#define VPECONTROL_TE_SHIFT 15
94 +#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
95 +#define VPECONTROL_EXCPT_SHIFT 16
96 +#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
97 +
98 +/* Thread Exception Codes for EXCPT field */
99 +#define THREX_TU 0
100 +#define THREX_TO 1
101 +#define THREX_IYQ 2
102 +#define THREX_GSX 3
103 +#define THREX_YSCH 4
104 +#define THREX_GSSCH 5
105 +
106 +#define VPECONTROL_GSI_SHIFT 20
107 +#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
108 +#define VPECONTROL_YSI_SHIFT 21
109 +#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
110 +
111 +/* VPEConf0 fields (per VPE) */
112 +#define VPECONF0_VPA_SHIFT 0
113 +#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
114 +#define VPECONF0_MVP_SHIFT 1
115 +#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
116 +#define VPECONF0_XTC_SHIFT 21
117 +#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
118 +
119 +/* VPEConf1 fields (per VPE) */
120 +#define VPECONF1_NCP1_SHIFT 0
121 +#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
122 +#define VPECONF1_NCP2_SHIFT 10
123 +#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
124 +#define VPECONF1_NCX_SHIFT 20
125 +#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
126 +
127 +/* TCStatus fields (per TC) */
128 +#define TCSTATUS_TASID (_ULCAST_(0xff))
129 +#define TCSTATUS_IXMT_SHIFT 10
130 +#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
131 +#define TCSTATUS_TKSU_SHIFT 11
132 +#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
133 +#define TCSTATUS_A_SHIFT 13
134 +#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
135 +#define TCSTATUS_DA_SHIFT 15
136 +#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
137 +#define TCSTATUS_DT_SHIFT 20
138 +#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
139 +#define TCSTATUS_TDS_SHIFT 21
140 +#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
141 +#define TCSTATUS_TSST_SHIFT 22
142 +#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
143 +#define TCSTATUS_RNST_SHIFT 23
144 +#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
145 +/* Codes for RNST */
146 +#define TC_RUNNING 0
147 +#define TC_WAITING 1
148 +#define TC_YIELDING 2
149 +#define TC_GATED 3
150 +
151 +#define TCSTATUS_TMX_SHIFT 27
152 +#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
153 +/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
154 +
155 +/* TCBind */
156 +#define TCBIND_CURVPE_SHIFT 0
157 +#define TCBIND_CURVPE (_ULCAST_(0xf))
158 +
159 +#define TCBIND_CURTC_SHIFT 21
160 +
161 +#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
162 +
163 +/* TCHalt */
164 +#define TCHALT_H (_ULCAST_(1))
165 +
166 +#endif
167 --
168 2.36.1
169
Staging tree of Sander Vanheule