1b41f9700241dcfd693efd2b8a685810399d7649
[openwrt/staging/blocktrron.git] /
1 From ee9002a825695b5dca76f758a9365ca7f7d18265 Mon Sep 17 00:00:00 2001
2 From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 Date: Wed, 4 May 2022 15:19:16 +0200
4 Subject: [PATCH] arm64: dts: qcom: correct DWC3 node names and unit addresses
5
6 Align DWC3 USB node names with DT schema ("usb" is expected) and correct
7 the unit addresses to match the "reg" property. This also implies
8 overriding nodes by label, instead of full path.
9
10 Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org
12 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 ---
14 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
15 1 file changed, 2 insertions(+), 2 deletions(-)
16
17 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
18 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
19 @@ -579,7 +579,7 @@
20 resets = <&gcc GCC_USB0_BCR>;
21 status = "disabled";
22
23 - dwc_0: dwc3@8a00000 {
24 + dwc_0: usb@8a00000 {
25 compatible = "snps,dwc3";
26 reg = <0x8a00000 0xcd00>;
27 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
28 @@ -619,7 +619,7 @@
29 resets = <&gcc GCC_USB1_BCR>;
30 status = "disabled";
31
32 - dwc_1: dwc3@8c00000 {
33 + dwc_1: usb@8c00000 {
34 compatible = "snps,dwc3";
35 reg = <0x8c00000 0xcd00>;
36 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;