236d6a217c50cb5639cd855054fb92e931f16218
[openwrt/staging/neocturne.git] /
1 From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001
2 From: Maso Huang <maso.huang@mediatek.com>
3 Date: Thu, 17 Aug 2023 18:13:38 +0800
4 Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe
5 document
6
7 Add mt7986 audio afe document.
8
9 Signed-off-by: Maso Huang <maso.huang@mediatek.com>
10 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com
12 Signed-off-by: Mark Brown <broonie@kernel.org>
13 ---
14 .../bindings/sound/mediatek,mt7986-afe.yaml | 160 ++++++++++++++++++
15 1 file changed, 160 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
17
18 --- /dev/null
19 +++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
20 @@ -0,0 +1,160 @@
21 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
22 +%YAML 1.2
23 +---
24 +$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
25 +$schema: http://devicetree.org/meta-schemas/core.yaml#
26 +
27 +title: MediaTek AFE PCM controller for MT7986
28 +
29 +maintainers:
30 + - Maso Huang <maso.huang@mediatek.com>
31 +
32 +properties:
33 + compatible:
34 + oneOf:
35 + - const: mediatek,mt7986-afe
36 + - items:
37 + - enum:
38 + - mediatek,mt7981-afe
39 + - mediatek,mt7988-afe
40 + - const: mediatek,mt7986-afe
41 +
42 + reg:
43 + maxItems: 1
44 +
45 + interrupts:
46 + maxItems: 1
47 +
48 + clocks:
49 + minItems: 5
50 + items:
51 + - description: audio bus clock
52 + - description: audio 26M clock
53 + - description: audio intbus clock
54 + - description: audio hopping clock
55 + - description: audio pll clock
56 + - description: mux for pcm_mck
57 + - description: audio i2s/pcm mck
58 +
59 + clock-names:
60 + minItems: 5
61 + items:
62 + - const: bus_ck
63 + - const: 26m_ck
64 + - const: l_ck
65 + - const: aud_ck
66 + - const: eg2_ck
67 + - const: sel
68 + - const: i2s_m
69 +
70 +required:
71 + - compatible
72 + - reg
73 + - interrupts
74 + - clocks
75 + - clock-names
76 +
77 +allOf:
78 + - if:
79 + properties:
80 + compatible:
81 + contains:
82 + const: mediatek,mt7986-afe
83 + then:
84 + properties:
85 + clocks:
86 + items:
87 + - description: audio bus clock
88 + - description: audio 26M clock
89 + - description: audio intbus clock
90 + - description: audio hopping clock
91 + - description: audio pll clock
92 + clock-names:
93 + items:
94 + - const: bus_ck
95 + - const: 26m_ck
96 + - const: l_ck
97 + - const: aud_ck
98 + - const: eg2_ck
99 +
100 + - if:
101 + properties:
102 + compatible:
103 + contains:
104 + const: mediatek,mt7981-afe
105 + then:
106 + properties:
107 + clocks:
108 + items:
109 + - description: audio bus clock
110 + - description: audio 26M clock
111 + - description: audio intbus clock
112 + - description: audio hopping clock
113 + - description: audio pll clock
114 + - description: mux for pcm_mck
115 + clock-names:
116 + items:
117 + - const: bus_ck
118 + - const: 26m_ck
119 + - const: l_ck
120 + - const: aud_ck
121 + - const: eg2_ck
122 + - const: sel
123 +
124 + - if:
125 + properties:
126 + compatible:
127 + contains:
128 + const: mediatek,mt7988-afe
129 + then:
130 + properties:
131 + clocks:
132 + items:
133 + - description: audio bus clock
134 + - description: audio 26M clock
135 + - description: audio intbus clock
136 + - description: audio hopping clock
137 + - description: audio pll clock
138 + - description: mux for pcm_mck
139 + - description: audio i2s/pcm mck
140 + clock-names:
141 + items:
142 + - const: bus_ck
143 + - const: 26m_ck
144 + - const: l_ck
145 + - const: aud_ck
146 + - const: eg2_ck
147 + - const: sel
148 + - const: i2s_m
149 +
150 +additionalProperties: false
151 +
152 +examples:
153 + - |
154 + #include <dt-bindings/interrupt-controller/arm-gic.h>
155 + #include <dt-bindings/interrupt-controller/irq.h>
156 + #include <dt-bindings/clock/mt7986-clk.h>
157 +
158 + afe@11210000 {
159 + compatible = "mediatek,mt7986-afe";
160 + reg = <0x11210000 0x9000>;
161 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
162 + clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
163 + <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
164 + <&infracfg_ao CLK_INFRA_AUD_L_CK>,
165 + <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
166 + <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
167 + clock-names = "bus_ck",
168 + "26m_ck",
169 + "l_ck",
170 + "aud_ck",
171 + "eg2_ck";
172 + assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
173 + <&topckgen CLK_TOP_AUD_L_SEL>,
174 + <&topckgen CLK_TOP_A_TUNER_SEL>;
175 + assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
176 + <&apmixedsys CLK_APMIXED_APLL2>,
177 + <&topckgen CLK_TOP_APLL2_D4>;
178 + };
179 +
180 +...