28cfc9d2d8070cf54b1f768f568d168f4202fbee
[openwrt/staging/blogic.git] /
1 This patch is a partial backport of commit ef01c6c36bb8 ("ARM: mvebu:
2 remove Armada 375 Z1 workaround for I/O coherency"). This commit was
3 merged in v3.19, so kernel versions later than v3.19 are not affected
4 by the problem that this commit fixes.
5
6 It does not make a lot of sense to backport this commit entirely,
7 since it is mainly removing some no longer useful code. However, this
8 commit is also making sure that the bus_register_notifier that
9 register the custom DMA operations that should be used for HW I/O
10 coherency does not get registered when said HW I/O coherency is not
11 enabled.
12
13 This is particularly critical since we have decided to disable HW I/O
14 coherency completely in all kernels < 4.0, to be on the safe side,
15 while experimenting a new implementation of the HW I/O coherency in >=
16 4.0.
17
18 Without this commit, kernels earlier than 3.18 have the custom DMA
19 operations normally used for HW I/O coherency registered (they don't
20 do cache maintenance operations), while HW I/O coherency is
21 disabled. It essentially causes every DMA transfer to transfer
22 garbage.
23
24 The issue fixed by this commit was introduced by 5ab5afd8ba83 ("ARM:
25 mvebu: implement Armada 375 coherency workaround"), but it was not
26 visible until now since it didn't cause any problem when HW I/O
27 coherency is enabled.
28
29 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
30 Cc: <stable@vger.kernel.org> v3.16..v3.18
31 ---
32 arch/arm/mach-mvebu/coherency.c | 5 +++--
33 1 file changed, 3 insertions(+), 2 deletions(-)
34
35 --- a/arch/arm/mach-mvebu/coherency.c
36 +++ b/arch/arm/mach-mvebu/coherency.c
37 @@ -391,8 +391,9 @@ static int __init coherency_late_init(vo
38 armada_375_coherency_init_wa();
39 }
40
41 - bus_register_notifier(&platform_bus_type,
42 - &mvebu_hwcc_nb);
43 + if (coherency_available())
44 + bus_register_notifier(&platform_bus_type,
45 + &mvebu_hwcc_nb);
46
47 return 0;
48 }