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1 From ce14be51d71bf39893786d380cbb82e81d2a10d5 Mon Sep 17 00:00:00 2001
2 From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.org>
3 Date: Wed, 14 Jul 2021 09:32:49 +0100
4 Subject: [PATCH] Add new "pispbe" driver (though not yet the Makesfiles or DT
5 required to use it)
6
7 media: bcm2712: Initial commit of the PiSP BE driver
8
9 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
10
11 media: bcm2712_pisp_be: PiSP driver updates.
12
13 - Start registering video nodes from /dev/video20
14 - Formatting fixes
15 - Define MODULE_DEVICE_TABLE() to probe correctly
16
17 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
18
19 media: pisp_be: Improve image format support
20
21 Add a new format table that lists the V4L2 format enums and their properties.
22 Keep the exising 'RPBP' format to support the userland verification tools.
23 This format requires userland to fill all plane properties. Standard V4L2
24 formats will derive these properties from the format table.
25
26 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
27
28 media: pisp_be: Advertise the meta output format explictily.
29
30 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
31
32 drivers: pisp_be: Various updates and cleanups
33
34 - Switch to a single node group for now.
35 - Add a node description table to simplify node handling.
36 - Switch HoG output to V4L2_CAP_META_CAPTURE type.
37 - Use string descriptions for node names in logging messages.
38
39 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
40
41 pisp_be: Updates for libcamera usage:
42
43 - Remove indexes from device entity names
44 - Add enumframesize and enumfmts ioctls
45 - Add default format to all nodes.
46
47 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
48
49 v4l2: pisp_be: Move format definitions into v4l2 core
50
51 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
52
53 media: raspberrypi: Move PiSP common headers to a single location
54
55 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
56
57 media: raspberrypi: Remove old pispbe driver.
58
59 This is now supersede by the driver in drivers/media/platform/raspberrypi/
60
61 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
62
63 PISP-BE Driver: Automate buffer-cycling for TDN and Stitch state.
64 Remove "tdn-input" and "stitch-input" nodes altogether (the output
65 nodes must still be opened and REQBUFS called with 1 or 2 buffers).
66 Also, a bit of tidying of buffer address handling and locking.
67
68 PISP-BE driver: Turn debug level right down to reduce overly-chatty messages
69
70 media: bcm2712: Depend on CONFIG_PM
71
72 Depend on CONFIG_PM as the driver uses the runtime_pm infrastructure.
73
74 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
75
76 drivers: media: pisp_be: Move BE driver to a raspberrypi directory
77
78 Move the pisp_be driver from drivers/media/platform/raspberrypi/ to
79 drivers/media/platform/raspberrypi/pisp_be/. This seems the accepted
80 convention in the drivers/media/platform/ directory structure.
81
82 Also rename the driver module from bcm2712_pisp_be to pisp_be.
83
84 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
85
86 pisp_be: Updates for libcamera streaming:
87
88 - Add some required v4l2 formats
89 - Add buf_prepare ioctl
90 - Set plane offsets correctly before reprogramming
91
92 pisp_be: Reduce logging verbosity
93
94 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
95
96 pisp_be: Add buffer timestamps
97
98 While at it, remove duplicate code when checking if the HW has completed
99 multiple jobs.
100
101 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
102
103 pisp_be: Remove queue size allocation constraint
104
105 PISP-BE driver: Fix ISR to handle multiple done/start events.
106
107 PISP-BE: Fix variable-name shadowing bugette
108
109 PISP-BE: Support for two node groups. Reorganize the driver.
110
111 To support 2 concurrent libcamera applications, we need 2 node groups,
112 need to allow multiple opens of each node (because libcamera does this)
113 and create a separate media device per group (to support file-locking).
114
115 This triggered significant rearrangement of the driver. Some calls
116 that we formerly intercepted have been delegated back to v4l2/vb2.
117 Logging changes arising from multiple v4l2_dev. Refactored probe()
118 and initialization. Avoid dynamically-allocated entity name strings.
119
120 drivers: media: pisp_be: Add vidioc_enum_fmt_meta_out
121
122 This was missing in the struct v4l2_ioctl_ops definition.
123
124 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
125
126 drivers: media: pispe_be: Add Bayer compressed formats
127
128 Add PiSP Bayer compressed formats to the list of supported pixel formats
129 for the PiSP backend driver.
130
131 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
132
133 drivers: meida: pisp_be: Fix overflow in plane size calculations
134
135 The calculations for buffer plane sizes can overflow because of the
136 plane factor shift. Fix this by using u64 integers for the calculations.
137
138 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
139
140 drivers: media: pisp_be: Use 0P3 for plane factors
141
142 Use less precision for the plane factors to avoid any nasty overflows.
143
144 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
145
146 media: pisp: Checkpatch and coding style fixups
147
148 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
149
150 media: pisp_be: More coding style fixups
151
152 media: platform: bcm2712: pisp_be: Fix crash when buffer format not set
153
154 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
155
156 media: platform: bcm2712: pisp_be: Allow non-SRGB colour spaces on RGB outputs
157
158 Allow colour spaces other than SRGB when the output format in question
159 is an RGB output. This commit merely ports over existing changes from
160 the vc4 ISP driver.
161
162 Signed-off-by: David Plowman <david.plowman@raspberrypi.com>
163
164 media: platform: bcm2712: Tweak list of BE supported image formats
165
166 Remove RGB565 and 10- and 12-bit packed raw formats, which ISP-BE
167 can't support for input or output. Add NV12M and NV21M which it can.
168 (I didn't bother adding YUV422P, which apparently is not widely used.)
169
170 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
171
172 pisp_be: Fill the hardware revision in the media entity struct
173
174 This can be used by userland to determine the hardware capabilities.
175
176 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
177
178 bcm2712: Use BIT() macro
179
180 Use the BIT() macro instead of plain bit shifting.
181
182 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
183
184 bcm2712: Invert condition in pispbe_schedule_internal()
185
186 Return earlier and save one indentation level
187
188 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
189
190 bcm2712: Invert condition in for loop
191
192 Save one indentation level by continuing if the node is not streaming.
193
194 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
195
196 bcm2712: Do not declare a local variable
197
198 There already is a truct pispbe_node *node in the function scope.
199
200 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
201
202 bcm21712: Siplify pispbe_schedule_one()
203
204 A little more verbose but easier to follow ?
205
206 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
207
208 bcm2712: Rename pispbe_schedule_all() to pispbe_schedule_any()
209
210 The pispbe_schedule_all() function name is misleading, as the function
211 schedule a single job from any of the node groups. Rename it.
212
213 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
214
215 media: platform: bcm2712: Remove buffer auto-cycling from ISP-BE
216
217 Previously, the ISP-BE driver tried to automate "ping pong" buffers
218 for TDN and HDR state, but did not fully conceal them from users.
219
220 The automation has been removed: there are now separate output and
221 capture queues for each of TDN and Stitch, which must be managed by
222 user code (DMABUFs may be used to circulate buffers between queues).
223
224 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
225
226 drivers: media: pisp_be: Cache BE config buffer vaddr
227
228 When programming a new job, we access at the config buffer, possibly
229 from ISR context. So fetch and the virtual address when queuing the
230 buffer.
231
232 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
233
234 drivers: media: pisp_be: Remove all traces of ctrls and request API
235
236 These APIs are not (and will not) be used by the driver, so remove them.
237
238 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
239
240 media: bcm2712: Replace v4l2_dbg with dev_dbg
241
242 Replace the v4l2 debug helpers with the device debug once, which are
243 preferred.
244
245 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
246
247 media: bcm2712: Remove of_match_ptr()
248
249 The of_match_ptr() usage could cause a compiler warning if
250 CONFIG_OF is not enabled, as the pispbe_of_match variable would
251 result unused.
252
253 As the of_match_table field of struct platform_driver exists
254 unconditionally, drop of_match_ptr() to avoid a warning.
255
256 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
257
258 drivers: media: pispbe: Add local config buffer DMA allocation
259
260 When initialiasing the driver, allocate a number of tiles + config
261 structures used for storing hardware config internally in the driver.
262
263 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
264
265 drivers: media: pispbe: Use local config buffers
266
267 Store a copy of the config + tiles buffer locally when the buffer gets
268 queued. This resolves the security issue where a userland process may
269 modify the config buffer after it has been queued.
270
271 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
272
273 drivers: media: pispbe: Validate config buffers
274
275 Perform a basic config validation on the device output nodes to ensure
276 the buffer size and stride values do not result in a buffer overrun.
277
278 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
279
280 media: bcm2712: Rework probe sequence order
281
282 Rework the probe sequence to:
283 1) Use dev_err_probe() when failing to get clocks
284 2) Disable clock on error path
285 3) Disable the node groups if they have been enabled and
286 propagate the error up
287
288 Also disable clocks in the remove() function.
289
290 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
291
292 media: bcm2712: Use pm_runtime_ops
293
294 Introduce usage of runtime resume and suspend operations.
295
296 The diver only uses a single clock source which is enable/disabled
297 at resume and suspend time.
298
299 Implement file open and release operations to control enablement of
300 the clock provider.
301
302 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
303
304 media: bcm2712: Demote info message
305
306 Demote info message about clock enablement to dev_dbg()
307
308 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
309
310 media: bcm2712: Move pm_runtime calls to streamon/streamoff
311
312 Move the calls to pm_runtime_resume_and_get() and pm_runtime_put()
313 to the streamon and streamoff ioctl handlers.
314
315 Remove custom handlers for the open and close file operations and use
316 the framework provided helpers.
317
318 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
319
320 media: bcm2712: Use pm_runtime_autosuspend()
321
322 Use the _autosuspend() version of runtime_pm_put() in order to avoid
323 resuming and suspending the peripheral in between streaming sessions
324 closely apart one from the other.
325
326 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
327
328 drivers: media: pisp_be: Conditionally check buffers when preparing jobs
329
330 When preparing a job, check the global enables in the config structure
331 to see if the Output0/1, Tdn and Stitch blocks are enabled, and only
332 test for a buffer queued if they are.
333
334 This will allow userland to control the outputs selectively without
335 disabling/re-enabling the respective device nodes.
336
337 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
338
339 media: bcm2712: Rework media controller registration
340
341 The current implementation register the v4l2_device and the video
342 devices first, then creates the media controller and manually registers
343 entities there.
344
345 Rework the registration procedure to first create the v4l2_device and
346 register the media_device with it. Then create the video nodes which
347 gets automatically registered in the media graph by the core.
348
349 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
350
351 media: bcm2712: Create v4l2_subdev for ISP entity
352
353 Create a v4l2 subdevice to represent the PISPBE ISP entity.
354
355 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
356
357 media: bcm2712: Fix v4l2-compliance warn on QUERYCAP
358
359 Fix:
360
361 warn: v4l2-compliance.cpp(669): media bus_info
362 'platform:1000880000.pisp_be' differs from V4L2 bus_info
363 'platform:pispbe'
364
365 by populating the driver caps bus_info by using dev_name().
366
367 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
368
369 media: bcm2712: Fix v4l2-compliance warn on invalid pixfmt
370
371 The V4L2 API for the TRY_FMT/S_FMT ioctl allows the ioctl handler to
372 return an error code only in specific conditions. If an invalid pixel
373 format is supplied it should be adjusted instead of an error being
374 returned.
375
376 Albeit, v4l2-compliance treats this situation as a warning and not as
377 an error because the behaviour has been discussed in length in the past.
378
379 warn: v4l2-test-formats.cpp(794): TRY_FMT cannot handle an invalid pixelformat.
380 warn: v4l2-test-formats.cpp(795): This may or may not be a problem. For more information see:
381 warn: v4l2-test-formats.cpp(796): http://www.mail-archive.com/linux-media@vger.kernel.org/msg56550.html
382 VIDIOC_TRY_FMT returned -1 (Invalid argument)
383
384 Regardless of the warning vs failure decision, adjust the try_format()
385 function implementation to use V4L2_PIX_FMT_YUV420M as default pixel
386 format if the supplied one is invalid.
387
388 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
389
390 media: bcm2712: Fix v4l2-compliance warn on HOG pix format
391
392 The try_format() implementation for the HOG video device node returns
393 an error if the supplied pixel format is not correct.
394
395 As per the video device output and capture video nodes, this contradicts
396 the V4L2 specification even if it is treated as a warning by
397 v4l2-compliance.
398
399 Fix this by forcing the buffer pixel format and size to the default
400 supported one. While at here, use the BIT() macro in the format
401 initialization function.
402
403 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
404
405 media: bcm2712: Fix formats enumeration
406
407 Right now a single implementation of enum_fmt() is used for all nodes
408 in a group. This means that all the BE supported formats are listed for
409 all the nodes. This is incorrect as the meta capture and output node
410 formats should be restricted, and the meta formats should not be
411 enumerated for video output and capture devices.
412
413 Fix this by restricting the enumeration of META formats to the config
414 and hog nodes. Split out from the list of supported_formats the
415 V4L2_META_FMT_RPI_BE_CFG which is only used for the meta_out node, while
416 V4L2_PIX_FMT_RPI_BE is kept in the list of supported_formats as it can
417 be used as an opaque format for both meta_cap, video_cap and video_out
418 nodes.
419
420 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
421
422 media: bcm2712: Minor fixes to support PiSP regression tests
423
424 Allow RGB input, not just Bayer (but only of those at once);
425 Allow Wallpaper image formats. XXX They are not yet size-checked;
426 Set "chicken bits" to test BURST_TRIM and AXI AWID/BID variation.
427 Convert some v4l2_err() to dev_err()
428
429 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
430
431 drivers: media: pisp_be: Use the maximum number of config buffers
432
433 Set PISP_BE_NUM_CONFIG_BUFFERS the the maximum number of possible
434 buffers. In the worst case, this overallocates config buffers, but
435 given their size, it's not too much of a problem.
436
437 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
438
439 media: pisp_be: Fix extra PM runtime put
440
441 vidioc_streamoff callback can be called even if vidioc_streamon was
442 never called. The driver currently does PM runtime get/put in these
443 callbacks, which may lead to a put without a matching get.
444
445 Fix this by moving the PM runtime get/put to vb2_ops's start_streaming &
446 stop_streaming, which the framework makes sure won't get extra calls.
447
448 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
449
450 drivers: media: pisp_be: Don't report V4L2_PIX_FMT_RPI_BE format
451
452 This is an internal opaque format, not to be reported in enum_fmt.
453
454 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
455 ---
456 drivers/media/platform/Kconfig | 1 +
457 drivers/media/platform/Makefile | 1 +
458 drivers/media/platform/raspberrypi/Kconfig | 5 +
459 drivers/media/platform/raspberrypi/Makefile | 3 +
460 .../platform/raspberrypi/pisp_be/Kconfig | 12 +
461 .../platform/raspberrypi/pisp_be/Makefile | 6 +
462 .../platform/raspberrypi/pisp_be/pisp_be.c | 1985 +++++++++++++++++
463 .../raspberrypi/pisp_be/pisp_be_config.h | 533 +++++
464 .../raspberrypi/pisp_be/pisp_be_formats.h | 469 ++++
465 drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
466 include/media/raspberrypi/pisp_common.h | 65 +
467 include/media/raspberrypi/pisp_types.h | 144 ++
468 include/uapi/linux/videodev2.h | 6 +
469 13 files changed, 3232 insertions(+)
470 create mode 100644 drivers/media/platform/raspberrypi/Kconfig
471 create mode 100644 drivers/media/platform/raspberrypi/Makefile
472 create mode 100644 drivers/media/platform/raspberrypi/pisp_be/Kconfig
473 create mode 100644 drivers/media/platform/raspberrypi/pisp_be/Makefile
474 create mode 100644 drivers/media/platform/raspberrypi/pisp_be/pisp_be.c
475 create mode 100644 drivers/media/platform/raspberrypi/pisp_be/pisp_be_config.h
476 create mode 100644 drivers/media/platform/raspberrypi/pisp_be/pisp_be_formats.h
477 create mode 100644 include/media/raspberrypi/pisp_common.h
478 create mode 100644 include/media/raspberrypi/pisp_types.h
479
480 --- a/drivers/media/platform/Kconfig
481 +++ b/drivers/media/platform/Kconfig
482 @@ -76,6 +76,7 @@ source "drivers/media/platform/mediatek/
483 source "drivers/media/platform/nvidia/Kconfig"
484 source "drivers/media/platform/nxp/Kconfig"
485 source "drivers/media/platform/qcom/Kconfig"
486 +source "drivers/media/platform/raspberrypi/Kconfig"
487 source "drivers/media/platform/renesas/Kconfig"
488 source "drivers/media/platform/rockchip/Kconfig"
489 source "drivers/media/platform/samsung/Kconfig"
490 --- a/drivers/media/platform/Makefile
491 +++ b/drivers/media/platform/Makefile
492 @@ -19,6 +19,7 @@ obj-y += mediatek/
493 obj-y += nvidia/
494 obj-y += nxp/
495 obj-y += qcom/
496 +obj-y += raspberrypi/
497 obj-y += renesas/
498 obj-y += rockchip/
499 obj-y += samsung/
500 --- /dev/null
501 +++ b/drivers/media/platform/raspberrypi/Kconfig
502 @@ -0,0 +1,5 @@
503 +# SPDX-License-Identifier: GPL-2.0-only
504 +
505 +comment "Raspberry Pi media platform drivers"
506 +
507 +source "drivers/media/platform/raspberrypi/pisp_be/Kconfig"
508 --- /dev/null
509 +++ b/drivers/media/platform/raspberrypi/Makefile
510 @@ -0,0 +1,3 @@
511 +# SPDX-License-Identifier: GPL-2.0
512 +
513 +obj-y += pisp_be/
514 --- /dev/null
515 +++ b/drivers/media/platform/raspberrypi/pisp_be/Kconfig
516 @@ -0,0 +1,12 @@
517 +config VIDEO_RASPBERRYPI_PISP_BE
518 + tristate "Raspberry Pi PiSP Backend (BE) ISP driver"
519 + depends on VIDEO_DEV && PM
520 + select VIDEO_V4L2_SUBDEV_API
521 + select MEDIA_CONTROLLER
522 + select VIDEOBUF2_DMA_CONTIG
523 + select V4L2_FWNODE
524 + help
525 + Say Y here to enable support for the PiSP Backend (BE) ISP driver.
526 +
527 + To compile this driver as a module, choose M here. The module will be
528 + called pisp-be.
529 --- /dev/null
530 +++ b/drivers/media/platform/raspberrypi/pisp_be/Makefile
531 @@ -0,0 +1,6 @@
532 +# SPDX-License-Identifier: GPL-2.0
533 +#
534 +# Makefile for Raspberry Pi PiSP Backend driver
535 +#
536 +pisp-be-objs := pisp_be.o
537 +obj-$(CONFIG_VIDEO_RASPBERRYPI_PISP_BE) += pisp-be.o
538 --- /dev/null
539 +++ b/drivers/media/platform/raspberrypi/pisp_be/pisp_be.c
540 @@ -0,0 +1,1985 @@
541 +// SPDX-License-Identifier: GPL-2.0
542 +/*
543 + * PiSP Back End driver.
544 + * Copyright (c) 2021-2022 Raspberry Pi Limited.
545 + *
546 + */
547 +#include <linux/clk.h>
548 +#include <linux/interrupt.h>
549 +#include <linux/io.h>
550 +#include <linux/module.h>
551 +#include <linux/platform_device.h>
552 +#include <linux/pm_runtime.h>
553 +#include <media/v4l2-device.h>
554 +#include <media/v4l2-ioctl.h>
555 +#include <media/videobuf2-dma-contig.h>
556 +#include <media/videobuf2-vmalloc.h>
557 +
558 +#include "pisp_be_config.h"
559 +#include "pisp_be_formats.h"
560 +
561 +MODULE_DESCRIPTION("PiSP Back End driver");
562 +MODULE_AUTHOR("David Plowman <david.plowman@raspberrypi.com>");
563 +MODULE_AUTHOR("Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>");
564 +MODULE_LICENSE("GPL v2");
565 +
566 +/* Offset to use when registering the /dev/videoX node */
567 +#define PISPBE_VIDEO_NODE_OFFSET 20
568 +
569 +/* Maximum number of config buffers possible */
570 +#define PISP_BE_NUM_CONFIG_BUFFERS VB2_MAX_FRAME
571 +
572 +/*
573 + * We want to support 2 independent instances allowing 2 simultaneous users
574 + * of the ISP-BE (of course they share hardware, platform resources and mutex).
575 + * Each such instance comprises a group of device nodes representing input
576 + * and output queues, and a media controller device node to describe them.
577 + */
578 +#define PISPBE_NUM_NODE_GROUPS 2
579 +
580 +#define PISPBE_NAME "pispbe"
581 +
582 +/* Some ISP-BE registers */
583 +#define PISP_BE_VERSION_OFFSET (0x0)
584 +#define PISP_BE_CONTROL_OFFSET (0x4)
585 +#define PISP_BE_TILE_ADDR_LO_OFFSET (0x8)
586 +#define PISP_BE_TILE_ADDR_HI_OFFSET (0xc)
587 +#define PISP_BE_STATUS_OFFSET (0x10)
588 +#define PISP_BE_BATCH_STATUS_OFFSET (0x14)
589 +#define PISP_BE_INTERRUPT_EN_OFFSET (0x18)
590 +#define PISP_BE_INTERRUPT_STATUS_OFFSET (0x1c)
591 +#define PISP_BE_AXI_OFFSET (0x20)
592 +#define PISP_BE_CONFIG_BASE_OFFSET (0x40)
593 +#define PISP_BE_IO_INPUT_ADDR0_LO_OFFSET (PISP_BE_CONFIG_BASE_OFFSET)
594 +#define PISP_BE_GLOBAL_BAYER_ENABLE_OFFSET (PISP_BE_CONFIG_BASE_OFFSET + 0x70)
595 +#define PISP_BE_GLOBAL_RGB_ENABLE_OFFSET (PISP_BE_CONFIG_BASE_OFFSET + 0x74)
596 +#define N_HW_ADDRESSES 14
597 +#define N_HW_ENABLES 2
598 +
599 +#define PISP_BE_VERSION_2712C1 0x02252700
600 +#define PISP_BE_VERSION_MINOR_BITS 0xF
601 +
602 +/*
603 + * This maps our nodes onto the inputs/outputs of the actual PiSP Back End.
604 + * Be wary of the word "OUTPUT" which is used ambiguously here. In a V4L2
605 + * context it means an input to the hardware (source image or metadata).
606 + * Elsewhere it means an output from the hardware.
607 + */
608 +enum node_ids {
609 + MAIN_INPUT_NODE,
610 + TDN_INPUT_NODE,
611 + STITCH_INPUT_NODE,
612 + HOG_OUTPUT_NODE,
613 + OUTPUT0_NODE,
614 + OUTPUT1_NODE,
615 + TDN_OUTPUT_NODE,
616 + STITCH_OUTPUT_NODE,
617 + CONFIG_NODE,
618 + PISPBE_NUM_NODES
619 +};
620 +
621 +struct node_description {
622 + const char *ent_name;
623 + enum v4l2_buf_type buf_type;
624 + unsigned int caps;
625 +};
626 +
627 +static const struct node_description node_desc[PISPBE_NUM_NODES] = {
628 + /* MAIN_INPUT_NODE */
629 + {
630 + .ent_name = PISPBE_NAME "-input",
631 + .buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
632 + .caps = V4L2_CAP_VIDEO_OUTPUT_MPLANE,
633 + },
634 + /* TDN_INPUT_NODE */
635 + {
636 + .ent_name = PISPBE_NAME "-tdn_input",
637 + .buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
638 + .caps = V4L2_CAP_VIDEO_OUTPUT_MPLANE,
639 + },
640 + /* STITCH_INPUT_NODE */
641 + {
642 + .ent_name = PISPBE_NAME "-stitch_input",
643 + .buf_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
644 + .caps = V4L2_CAP_VIDEO_OUTPUT_MPLANE,
645 + },
646 + /* HOG_OUTPUT_NODE */
647 + {
648 + .ent_name = PISPBE_NAME "-hog_output",
649 + .buf_type = V4L2_BUF_TYPE_META_CAPTURE,
650 + .caps = V4L2_CAP_META_CAPTURE,
651 + },
652 + /* OUTPUT0_NODE */
653 + {
654 + .ent_name = PISPBE_NAME "-output0",
655 + .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
656 + .caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
657 + },
658 + /* OUTPUT1_NODE */
659 + {
660 + .ent_name = PISPBE_NAME "-output1",
661 + .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
662 + .caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
663 + },
664 + /* TDN_OUTPUT_NODE */
665 + {
666 + .ent_name = PISPBE_NAME "-tdn_output",
667 + .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
668 + .caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
669 + },
670 + /* STITCH_OUTPUT_NODE */
671 + {
672 + .ent_name = PISPBE_NAME "-stitch_output",
673 + .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
674 + .caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
675 + },
676 + /* CONFIG_NODE */
677 + {
678 + .ent_name = PISPBE_NAME "-config",
679 + .buf_type = V4L2_BUF_TYPE_META_OUTPUT,
680 + .caps = V4L2_CAP_META_OUTPUT,
681 + }
682 +};
683 +
684 +#define NODE_DESC_IS_OUTPUT(desc) ( \
685 + ((desc)->buf_type == V4L2_BUF_TYPE_META_OUTPUT) || \
686 + ((desc)->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT) || \
687 + ((desc)->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE))
688 +
689 +#define NODE_IS_META(node) ( \
690 + ((node)->buf_type == V4L2_BUF_TYPE_META_OUTPUT) || \
691 + ((node)->buf_type == V4L2_BUF_TYPE_META_CAPTURE))
692 +#define NODE_IS_OUTPUT(node) ( \
693 + ((node)->buf_type == V4L2_BUF_TYPE_META_OUTPUT) || \
694 + ((node)->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT) || \
695 + ((node)->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE))
696 +#define NODE_IS_CAPTURE(node) ( \
697 + ((node)->buf_type == V4L2_BUF_TYPE_META_CAPTURE) || \
698 + ((node)->buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE) || \
699 + ((node)->buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
700 +#define NODE_IS_MPLANE(node) ( \
701 + ((node)->buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) || \
702 + ((node)->buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
703 +
704 +/*
705 + * Structure to describe a single node /dev/video<N> which represents a single
706 + * input or output queue to the PiSP Back End device.
707 + */
708 +struct pispbe_node {
709 + unsigned int id;
710 + int vfl_dir;
711 + enum v4l2_buf_type buf_type;
712 + struct video_device vfd;
713 + struct media_pad pad;
714 + struct media_intf_devnode *intf_devnode;
715 + struct media_link *intf_link;
716 + struct pispbe_node_group *node_group;
717 + struct mutex node_lock;
718 + struct mutex queue_lock;
719 + spinlock_t ready_lock;
720 + struct list_head ready_queue;
721 + struct vb2_queue queue;
722 + struct v4l2_format format;
723 + const struct pisp_be_format *pisp_format;
724 +};
725 +
726 +/* For logging only, use the entity name with "pispbe" and separator removed */
727 +#define NODE_NAME(node) \
728 + (node_desc[(node)->id].ent_name + sizeof(PISPBE_NAME))
729 +#define NODE_GET_V4L2(node) ((node)->node_group->v4l2_dev)
730 +
731 +/*
732 + * Node group structure, which comprises all the input and output nodes that a
733 + * single PiSP client will need, along with its own v4l2 and media devices.
734 + */
735 +struct pispbe_node_group {
736 + unsigned int id;
737 + struct v4l2_device v4l2_dev;
738 + struct v4l2_subdev sd;
739 + struct pispbe_dev *pispbe;
740 + struct media_device mdev;
741 + struct pispbe_node node[PISPBE_NUM_NODES];
742 + u32 streaming_map; /* bitmap of which nodes are streaming */
743 + struct media_pad pad[PISPBE_NUM_NODES]; /* output pads first */
744 + struct pisp_be_tiles_config *config;
745 + dma_addr_t config_dma_addr;
746 +};
747 +
748 +/* Records details of the jobs currently running or queued on the h/w. */
749 +struct pispbe_job {
750 + struct pispbe_node_group *node_group;
751 + /*
752 + * An array of buffer pointers - remember it's source buffers first,
753 + * then captures, then metadata last.
754 + */
755 + struct pispbe_buffer *buf[PISPBE_NUM_NODES];
756 +};
757 +
758 +/*
759 + * Structure representing the entire PiSP Back End device, comprising several
760 + * node groups which share platform resources and a mutex for the actual HW.
761 + */
762 +struct pispbe_dev {
763 + struct device *dev;
764 + struct pispbe_node_group node_group[PISPBE_NUM_NODE_GROUPS];
765 + int hw_busy; /* non-zero if a job is queued or is being started */
766 + struct pispbe_job queued_job, running_job;
767 + void __iomem *be_reg_base;
768 + struct clk *clk;
769 + int irq;
770 + u32 hw_version;
771 + u8 done, started;
772 + spinlock_t hw_lock; /* protects "hw_busy" flag and streaming_map */
773 +};
774 +
775 +static inline u32 read_reg(struct pispbe_dev *pispbe, unsigned int offset)
776 +{
777 + return readl(pispbe->be_reg_base + offset);
778 +}
779 +
780 +static inline void write_reg(struct pispbe_dev *pispbe, unsigned int offset,
781 + u32 val)
782 +{
783 + writel(val, pispbe->be_reg_base + offset);
784 +}
785 +
786 +/* Check and initialize hardware. */
787 +static int hw_init(struct pispbe_dev *pispbe)
788 +{
789 + u32 u;
790 +
791 + /* Check the HW is present and has a known version */
792 + u = read_reg(pispbe, PISP_BE_VERSION_OFFSET);
793 + dev_info(pispbe->dev, "pispbe_probe: HW version: 0x%08x", u);
794 + pispbe->hw_version = u;
795 + if ((u & ~PISP_BE_VERSION_MINOR_BITS) != PISP_BE_VERSION_2712C1)
796 + return -ENODEV;
797 +
798 + /* Clear leftover interrupts */
799 + write_reg(pispbe, PISP_BE_INTERRUPT_STATUS_OFFSET, 0xFFFFFFFFu);
800 + u = read_reg(pispbe, PISP_BE_BATCH_STATUS_OFFSET);
801 + dev_info(pispbe->dev, "pispbe_probe: BatchStatus: 0x%08x", u);
802 + pispbe->done = (uint8_t)u;
803 + pispbe->started = (uint8_t)(u >> 8);
804 + u = read_reg(pispbe, PISP_BE_STATUS_OFFSET);
805 + dev_info(pispbe->dev, "pispbe_probe: Status: 0x%08x", u);
806 + if (u != 0 || pispbe->done != pispbe->started) {
807 + dev_err(pispbe->dev, "pispbe_probe: HW is stuck or busy\n");
808 + return -EBUSY;
809 + }
810 + /*
811 + * AXI QOS=0, CACHE=4'b0010, PROT=3'b011
812 + * Also set "chicken bits" 22:20 which enable sub-64-byte bursts
813 + * and AXI AWID/BID variability (on versions which support this).
814 + */
815 + write_reg(pispbe, PISP_BE_AXI_OFFSET, 0x32703200u);
816 +
817 + /* Enable both interrupt flags */
818 + write_reg(pispbe, PISP_BE_INTERRUPT_EN_OFFSET, 0x00000003u);
819 + return 0;
820 +}
821 +
822 +/*
823 + * Queue a job to the h/w. If the h/w is idle it will begin immediately.
824 + * Caller must ensure it is "safe to queue", i.e. we don't already have a
825 + * queued, unstarted job.
826 + */
827 +static void hw_queue_job(struct pispbe_dev *pispbe,
828 + dma_addr_t hw_dma_addrs[N_HW_ADDRESSES],
829 + u32 hw_enables[N_HW_ENABLES],
830 + struct pisp_be_config *config, dma_addr_t tiles,
831 + unsigned int num_tiles)
832 +{
833 + unsigned int begin, end;
834 + unsigned int u;
835 +
836 + if (read_reg(pispbe, PISP_BE_STATUS_OFFSET) & 1)
837 + dev_err(pispbe->dev, "ERROR: not safe to queue new job!\n");
838 +
839 + /*
840 + * Write configuration to hardware. DMA addresses and enable flags
841 + * are passed separately, because the driver needs to sanitize them,
842 + * and we don't want to modify (or be vulnerable to modifications of)
843 + * the mmap'd buffer.
844 + */
845 + for (u = 0; u < N_HW_ADDRESSES; ++u) {
846 + write_reg(pispbe, PISP_BE_IO_INPUT_ADDR0_LO_OFFSET + 8 * u,
847 + (u32)(hw_dma_addrs[u]));
848 + write_reg(pispbe, PISP_BE_IO_INPUT_ADDR0_LO_OFFSET + 8 * u + 4,
849 + (u32)(hw_dma_addrs[u] >> 32));
850 + }
851 + write_reg(pispbe, PISP_BE_GLOBAL_BAYER_ENABLE_OFFSET, hw_enables[0]);
852 + write_reg(pispbe, PISP_BE_GLOBAL_RGB_ENABLE_OFFSET, hw_enables[1]);
853 +
854 + /*
855 + * Everything else is as supplied by the user. XXX Buffer sizes not
856 + * checked!
857 + */
858 + begin = offsetof(struct pisp_be_config, global.bayer_order) /
859 + sizeof(u32);
860 + end = offsetof(struct pisp_be_config, axi) / sizeof(u32);
861 + for (u = begin; u < end; u++) {
862 + unsigned int val = ((u32 *)config)[u];
863 +
864 + write_reg(pispbe, PISP_BE_CONFIG_BASE_OFFSET + 4 * u, val);
865 + }
866 +
867 + /* Read back the addresses -- an error here could be fatal */
868 + for (u = 0; u < N_HW_ADDRESSES; ++u) {
869 + unsigned int offset = PISP_BE_IO_INPUT_ADDR0_LO_OFFSET + 8 * u;
870 + u64 along = read_reg(pispbe, offset);
871 +
872 + along += ((u64)read_reg(pispbe, offset + 4)) << 32;
873 + if (along != (u64)(hw_dma_addrs[u])) {
874 + dev_err(pispbe->dev,
875 + "ISP BE config error: check if ISP RAMs enabled?\n");
876 + return;
877 + }
878 + }
879 +
880 + /*
881 + * Write tile pointer to hardware. XXX Tile offsets and sizes not
882 + * checked (and even if checked, the user could subsequently modify
883 + * them)!
884 + */
885 + write_reg(pispbe, PISP_BE_TILE_ADDR_LO_OFFSET, (u32)tiles);
886 + write_reg(pispbe, PISP_BE_TILE_ADDR_HI_OFFSET, (u32)(tiles >> 32));
887 +
888 + /* Enqueue the job */
889 + write_reg(pispbe, PISP_BE_CONTROL_OFFSET, 3 + 65536 * num_tiles);
890 +}
891 +
892 +struct pispbe_buffer {
893 + struct vb2_v4l2_buffer vb;
894 + struct list_head ready_list;
895 + unsigned int config_index;
896 +};
897 +
898 +static int get_addr_3(dma_addr_t addr[3], struct pispbe_buffer *buf,
899 + struct pispbe_node *node)
900 +{
901 + unsigned int num_planes = node->format.fmt.pix_mp.num_planes;
902 + unsigned int plane_factor = 0;
903 + unsigned int size;
904 + unsigned int p;
905 +
906 + if (!buf || !node->pisp_format)
907 + return 0;
908 +
909 + WARN_ON(!NODE_IS_MPLANE(node));
910 +
911 + /*
912 + * Determine the base plane size. This will not be the same
913 + * as node->format.fmt.pix_mp.plane_fmt[0].sizeimage for a single
914 + * plane buffer in an mplane format.
915 + */
916 + size = node->format.fmt.pix_mp.plane_fmt[0].bytesperline *
917 + node->format.fmt.pix_mp.height;
918 +
919 + for (p = 0; p < num_planes && p < 3; p++) {
920 + addr[p] = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, p);
921 + plane_factor += node->pisp_format->plane_factor[p];
922 + }
923 +
924 + for (; p < MAX_PLANES && node->pisp_format->plane_factor[p]; p++) {
925 + /*
926 + * Calculate the address offset of this plane as needed
927 + * by the hardware. This is specifically for non-mplane
928 + * buffer formats, where there are 3 image planes, e.g.
929 + * for the V4L2_PIX_FMT_YUV420 format.
930 + */
931 + addr[p] = addr[0] + ((size * plane_factor) >> 3);
932 + plane_factor += node->pisp_format->plane_factor[p];
933 + }
934 +
935 + return num_planes;
936 +}
937 +
938 +static dma_addr_t get_addr(struct pispbe_buffer *buf)
939 +{
940 + if (buf)
941 + return vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
942 + return 0;
943 +}
944 +
945 +static void
946 +fixup_addrs_enables(dma_addr_t addrs[N_HW_ADDRESSES],
947 + u32 hw_enables[N_HW_ENABLES],
948 + struct pisp_be_tiles_config *config,
949 + struct pispbe_buffer *buf[PISPBE_NUM_NODES],
950 + struct pispbe_node_group *node_group)
951 +{
952 + int ret, i;
953 +
954 + /* Take a copy of the "enable" bitmaps so we can modify them. */
955 + hw_enables[0] = config->config.global.bayer_enables;
956 + hw_enables[1] = config->config.global.rgb_enables;
957 +
958 + /*
959 + * Main input first. There are 3 address pointers, corresponding to up
960 + * to 3 planes.
961 + */
962 + ret = get_addr_3(addrs, buf[MAIN_INPUT_NODE],
963 + &node_group->node[MAIN_INPUT_NODE]);
964 + if (ret <= 0) {
965 + /*
966 + * This shouldn't happen; pispbe_schedule_internal should insist
967 + * on an input.
968 + */
969 + dev_warn(node_group->pispbe->dev,
970 + "ISP-BE missing input\n");
971 + hw_enables[0] = 0;
972 + hw_enables[1] = 0;
973 + return;
974 + }
975 +
976 + /*
977 + * Now TDN/Stitch inputs and outputs. These are single-plane and only
978 + * used with Bayer input. Input enables must match the requirements
979 + * of the processing stages, otherwise the hardware can lock up!
980 + */
981 + if (hw_enables[0] & PISP_BE_BAYER_ENABLE_INPUT) {
982 + addrs[3] = get_addr(buf[TDN_INPUT_NODE]);
983 + if (addrs[3] == 0 ||
984 + !(hw_enables[0] & PISP_BE_BAYER_ENABLE_TDN_INPUT) ||
985 + !(hw_enables[0] & PISP_BE_BAYER_ENABLE_TDN) ||
986 + (config->config.tdn.reset & 1)) {
987 + hw_enables[0] &= ~(PISP_BE_BAYER_ENABLE_TDN_INPUT |
988 + PISP_BE_BAYER_ENABLE_TDN_DECOMPRESS);
989 + if (!(config->config.tdn.reset & 1))
990 + hw_enables[0] &= ~PISP_BE_BAYER_ENABLE_TDN;
991 + }
992 +
993 + addrs[4] = get_addr(buf[STITCH_INPUT_NODE]);
994 + if (addrs[4] == 0 ||
995 + !(hw_enables[0] & PISP_BE_BAYER_ENABLE_STITCH_INPUT) ||
996 + !(hw_enables[0] & PISP_BE_BAYER_ENABLE_STITCH)) {
997 + hw_enables[0] &=
998 + ~(PISP_BE_BAYER_ENABLE_STITCH_INPUT |
999 + PISP_BE_BAYER_ENABLE_STITCH_DECOMPRESS |
1000 + PISP_BE_BAYER_ENABLE_STITCH);
1001 + }
1002 +
1003 + addrs[5] = get_addr(buf[TDN_OUTPUT_NODE]);
1004 + if (addrs[5] == 0)
1005 + hw_enables[0] &= ~(PISP_BE_BAYER_ENABLE_TDN_COMPRESS |
1006 + PISP_BE_BAYER_ENABLE_TDN_OUTPUT);
1007 +
1008 + addrs[6] = get_addr(buf[STITCH_OUTPUT_NODE]);
1009 + if (addrs[6] == 0)
1010 + hw_enables[0] &=
1011 + ~(PISP_BE_BAYER_ENABLE_STITCH_COMPRESS |
1012 + PISP_BE_BAYER_ENABLE_STITCH_OUTPUT);
1013 + } else {
1014 + /* No Bayer input? Disable entire Bayer pipe (else lockup) */
1015 + hw_enables[0] = 0;
1016 + }
1017 +
1018 + /* Main image output channels. */
1019 + for (i = 0; i < PISP_BACK_END_NUM_OUTPUTS; i++) {
1020 + ret = get_addr_3(addrs + 7 + 3 * i, buf[OUTPUT0_NODE + i],
1021 + &node_group->node[OUTPUT0_NODE + i]);
1022 + if (ret <= 0)
1023 + hw_enables[1] &= ~(PISP_BE_RGB_ENABLE_OUTPUT0 << i);
1024 + }
1025 +
1026 + /* HoG output (always single plane). */
1027 + addrs[13] = get_addr(buf[HOG_OUTPUT_NODE]);
1028 + if (addrs[13] == 0)
1029 + hw_enables[1] &= ~PISP_BE_RGB_ENABLE_HOG;
1030 +}
1031 +
1032 +/*
1033 + * Internal function. Called from pispbe_schedule_one/all. Returns non-zero if
1034 + * we started a job.
1035 + *
1036 + * Warning: needs to be called with hw_lock taken, and releases it if it
1037 + * schedules a job.
1038 + */
1039 +static int pispbe_schedule_internal(struct pispbe_node_group *node_group,
1040 + unsigned long flags)
1041 +{
1042 + struct pisp_be_tiles_config *config_tiles_buffer;
1043 + struct pispbe_dev *pispbe = node_group->pispbe;
1044 + struct pispbe_buffer *buf[PISPBE_NUM_NODES];
1045 + dma_addr_t hw_dma_addrs[N_HW_ADDRESSES];
1046 + dma_addr_t tiles;
1047 + u32 hw_enables[N_HW_ENABLES];
1048 + struct pispbe_node *node;
1049 + unsigned long flags1;
1050 + unsigned int config_index;
1051 + int i;
1052 +
1053 + /*
1054 + * To schedule a job, we need all streaming nodes (apart from Output0,
1055 + * Output1, Tdn and Stitch) to have a buffer ready, which must
1056 + * include at least a config buffer and a main input image.
1057 + *
1058 + * For Output0, Output1, Tdn and Stitch, a buffer only needs to be
1059 + * available if the blocks are enabled in the config.
1060 + *
1061 + * (Note that streaming_map is protected by hw_lock, which is held.)
1062 + */
1063 + if (((BIT(CONFIG_NODE) | BIT(MAIN_INPUT_NODE)) &
1064 + node_group->streaming_map) !=
1065 + (BIT(CONFIG_NODE) | BIT(MAIN_INPUT_NODE))) {
1066 + dev_dbg(pispbe->dev, "Nothing to do\n");
1067 + return 0;
1068 + }
1069 +
1070 + node = &node_group->node[CONFIG_NODE];
1071 + spin_lock_irqsave(&node->ready_lock, flags1);
1072 + buf[CONFIG_NODE] =
1073 + list_first_entry_or_null(&node->ready_queue, struct pispbe_buffer,
1074 + ready_list);
1075 + spin_unlock_irqrestore(&node->ready_lock, flags1);
1076 +
1077 + /* Exit early if no config buffer has been queued. */
1078 + if (!buf[CONFIG_NODE])
1079 + return 0;
1080 +
1081 + config_index = buf[CONFIG_NODE]->vb.vb2_buf.index;
1082 + config_tiles_buffer = &node_group->config[config_index];
1083 + tiles = (dma_addr_t)node_group->config_dma_addr +
1084 + config_index * sizeof(struct pisp_be_tiles_config) +
1085 + offsetof(struct pisp_be_tiles_config, tiles);
1086 +
1087 + /* remember: srcimages, captures then metadata */
1088 + for (i = 0; i < PISPBE_NUM_NODES; i++) {
1089 + unsigned int bayer_en =
1090 + config_tiles_buffer->config.global.bayer_enables;
1091 + unsigned int rgb_en =
1092 + config_tiles_buffer->config.global.rgb_enables;
1093 + bool ignore_buffers = false;
1094 +
1095 + /* Config node is handled outside the loop above. */
1096 + if (i == CONFIG_NODE)
1097 + continue;
1098 +
1099 + buf[i] = NULL;
1100 + if (!(node_group->streaming_map & BIT(i)))
1101 + continue;
1102 +
1103 + if ((!(rgb_en & PISP_BE_RGB_ENABLE_OUTPUT0) &&
1104 + i == OUTPUT0_NODE) ||
1105 + (!(rgb_en & PISP_BE_RGB_ENABLE_OUTPUT1) &&
1106 + i == OUTPUT1_NODE) ||
1107 + (!(bayer_en & PISP_BE_BAYER_ENABLE_TDN_INPUT) &&
1108 + i == TDN_INPUT_NODE) ||
1109 + (!(bayer_en & PISP_BE_BAYER_ENABLE_TDN_OUTPUT) &&
1110 + i == TDN_OUTPUT_NODE) ||
1111 + (!(bayer_en & PISP_BE_BAYER_ENABLE_STITCH_INPUT) &&
1112 + i == STITCH_INPUT_NODE) ||
1113 + (!(bayer_en & PISP_BE_BAYER_ENABLE_STITCH_OUTPUT) &&
1114 + i == STITCH_OUTPUT_NODE)) {
1115 + /*
1116 + * Ignore Output0/Output1/Tdn/Stitch buffer check if the
1117 + * global enables aren't set for these blocks. If a
1118 + * buffer has been provided, we dequeue it back to the
1119 + * user with the other in-use buffers.
1120 + *
1121 + */
1122 + ignore_buffers = true;
1123 + }
1124 +
1125 + node = &node_group->node[i];
1126 +
1127 + spin_lock_irqsave(&node->ready_lock, flags1);
1128 + buf[i] = list_first_entry_or_null(&node->ready_queue,
1129 + struct pispbe_buffer,
1130 + ready_list);
1131 + spin_unlock_irqrestore(&node->ready_lock, flags1);
1132 + if (!buf[i] && !ignore_buffers) {
1133 + dev_dbg(pispbe->dev, "Nothing to do\n");
1134 + return 0;
1135 + }
1136 + }
1137 +
1138 + /* Pull a buffer from each V4L2 queue to form the queued job */
1139 + for (i = 0; i < PISPBE_NUM_NODES; i++) {
1140 + if (buf[i]) {
1141 + node = &node_group->node[i];
1142 +
1143 + spin_lock_irqsave(&node->ready_lock, flags1);
1144 + list_del(&buf[i]->ready_list);
1145 + spin_unlock_irqrestore(&node->ready_lock,
1146 + flags1);
1147 + }
1148 + pispbe->queued_job.buf[i] = buf[i];
1149 + }
1150 +
1151 + pispbe->queued_job.node_group = node_group;
1152 + pispbe->hw_busy = 1;
1153 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1154 +
1155 + /*
1156 + * We can kick the job off without the hw_lock, as this can
1157 + * never run again until hw_busy is cleared, which will happen
1158 + * only when the following job has been queued.
1159 + */
1160 + dev_dbg(pispbe->dev, "Have buffers - starting hardware\n");
1161 +
1162 + /* Convert buffers to DMA addresses for the hardware */
1163 + fixup_addrs_enables(hw_dma_addrs, hw_enables,
1164 + config_tiles_buffer, buf, node_group);
1165 + /*
1166 + * This could be a spot to fill in the
1167 + * buf[i]->vb.vb2_buf.planes[j].bytesused fields?
1168 + */
1169 + i = config_tiles_buffer->num_tiles;
1170 + if (i <= 0 || i > PISP_BACK_END_NUM_TILES ||
1171 + !((hw_enables[0] | hw_enables[1]) &
1172 + PISP_BE_BAYER_ENABLE_INPUT)) {
1173 + /*
1174 + * Bad job. We can't let it proceed as it could lock up
1175 + * the hardware, or worse!
1176 + *
1177 + * XXX How to deal with this most cleanly? For now, just
1178 + * force num_tiles to 0, which causes the H/W to do
1179 + * something bizarre but survivable. It increments
1180 + * (started,done) counters by more than 1, but we seem
1181 + * to survive...
1182 + */
1183 + dev_err(pispbe->dev, "PROBLEM: Bad job");
1184 + i = 0;
1185 + }
1186 + hw_queue_job(pispbe, hw_dma_addrs, hw_enables,
1187 + &config_tiles_buffer->config, tiles, i);
1188 +
1189 + return 1;
1190 +}
1191 +
1192 +/* Try and schedule a job for just a single node group. */
1193 +static void pispbe_schedule_one(struct pispbe_node_group *node_group)
1194 +{
1195 + struct pispbe_dev *pispbe = node_group->pispbe;
1196 + unsigned long flags;
1197 + int ret;
1198 +
1199 + spin_lock_irqsave(&pispbe->hw_lock, flags);
1200 + if (pispbe->hw_busy) {
1201 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1202 + return;
1203 + }
1204 +
1205 + /* A non-zero return means the lock was released. */
1206 + ret = pispbe_schedule_internal(node_group, flags);
1207 + if (!ret)
1208 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1209 +}
1210 +
1211 +/* Try and schedule a job for any of the node groups. */
1212 +static void pispbe_schedule_any(struct pispbe_dev *pispbe, int clear_hw_busy)
1213 +{
1214 + unsigned long flags;
1215 +
1216 + spin_lock_irqsave(&pispbe->hw_lock, flags);
1217 +
1218 + if (clear_hw_busy)
1219 + pispbe->hw_busy = 0;
1220 + if (pispbe->hw_busy == 0) {
1221 + unsigned int i;
1222 +
1223 + for (i = 0; i < PISPBE_NUM_NODE_GROUPS; i++) {
1224 + /*
1225 + * A non-zero return from pispbe_schedule_internal means
1226 + * the lock was released.
1227 + */
1228 + if (pispbe_schedule_internal(&pispbe->node_group[i],
1229 + flags))
1230 + return;
1231 + }
1232 + }
1233 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1234 +}
1235 +
1236 +static void pispbe_isr_jobdone(struct pispbe_dev *pispbe,
1237 + struct pispbe_job *job)
1238 +{
1239 + struct pispbe_buffer **buf = job->buf;
1240 + u64 ts = ktime_get_ns();
1241 + int i;
1242 +
1243 + for (i = 0; i < PISPBE_NUM_NODES; i++) {
1244 + if (buf[i]) {
1245 + buf[i]->vb.vb2_buf.timestamp = ts;
1246 + vb2_buffer_done(&buf[i]->vb.vb2_buf,
1247 + VB2_BUF_STATE_DONE);
1248 + }
1249 + }
1250 +}
1251 +
1252 +static irqreturn_t pispbe_isr(int irq, void *dev)
1253 +{
1254 + struct pispbe_dev *pispbe = (struct pispbe_dev *)dev;
1255 + u8 started, done;
1256 + int can_queue_another = 0;
1257 + u32 u;
1258 +
1259 + u = read_reg(pispbe, PISP_BE_INTERRUPT_STATUS_OFFSET);
1260 + if (u == 0)
1261 + return IRQ_NONE;
1262 +
1263 + write_reg(pispbe, PISP_BE_INTERRUPT_STATUS_OFFSET, u);
1264 + dev_dbg(pispbe->dev, "Hardware interrupt\n");
1265 + u = read_reg(pispbe, PISP_BE_BATCH_STATUS_OFFSET);
1266 + done = (uint8_t)u;
1267 + started = (uint8_t)(u >> 8);
1268 + dev_dbg(pispbe->dev,
1269 + "H/W started %d done %d, previously started %d done %d\n",
1270 + (int)started, (int)done, (int)pispbe->started,
1271 + (int)pispbe->done);
1272 +
1273 + /*
1274 + * Be aware that done can go up by 2 and started by 1 when: a job that
1275 + * we previously saw "start" now finishes, and we then queued a new job
1276 + * which we see both start and finish "simultaneously".
1277 + */
1278 + if (pispbe->running_job.node_group && pispbe->done != done) {
1279 + pispbe_isr_jobdone(pispbe, &pispbe->running_job);
1280 + memset(&pispbe->running_job, 0, sizeof(pispbe->running_job));
1281 + pispbe->done++;
1282 + dev_dbg(pispbe->dev, "Job done (1)\n");
1283 + }
1284 +
1285 + if (pispbe->started != started) {
1286 + pispbe->started++;
1287 + can_queue_another = 1;
1288 + dev_dbg(pispbe->dev, "Job started\n");
1289 +
1290 + if (pispbe->done != done && pispbe->queued_job.node_group) {
1291 + pispbe_isr_jobdone(pispbe, &pispbe->queued_job);
1292 + pispbe->done++;
1293 + dev_dbg(pispbe->dev, "Job done (2)\n");
1294 + } else {
1295 + pispbe->running_job = pispbe->queued_job;
1296 + }
1297 +
1298 + memset(&pispbe->queued_job, 0, sizeof(pispbe->queued_job));
1299 + }
1300 +
1301 + if (pispbe->done != done || pispbe->started != started) {
1302 + dev_err(pispbe->dev, "PROBLEM: counters not matching!\n");
1303 + pispbe->started = started;
1304 + pispbe->done = done;
1305 + }
1306 +
1307 + /* check if there's more to do before going to sleep */
1308 + pispbe_schedule_any(pispbe, can_queue_another);
1309 +
1310 + return IRQ_HANDLED;
1311 +}
1312 +
1313 +static int pisp_be_validate_config(struct pispbe_node_group *node_group,
1314 + struct pisp_be_tiles_config *config)
1315 +{
1316 + u32 bayer_enables = config->config.global.bayer_enables;
1317 + u32 rgb_enables = config->config.global.rgb_enables;
1318 + struct device *dev = node_group->pispbe->dev;
1319 + struct v4l2_format *fmt;
1320 + unsigned int bpl, size, i, j;
1321 +
1322 + if (!(bayer_enables & PISP_BE_BAYER_ENABLE_INPUT) ==
1323 + !(rgb_enables & PISP_BE_RGB_ENABLE_INPUT)) {
1324 + dev_err(dev, "%s: Not one input enabled\n", __func__);
1325 + return -EIO;
1326 + }
1327 +
1328 + /* Ensure output config strides and buffer sizes match the V4L2 formats. */
1329 + fmt = &node_group->node[TDN_OUTPUT_NODE].format;
1330 + if (bayer_enables & PISP_BE_BAYER_ENABLE_TDN_OUTPUT) {
1331 + bpl = config->config.tdn_output_format.stride;
1332 + size = bpl * config->config.tdn_output_format.height;
1333 + if (fmt->fmt.pix_mp.plane_fmt[0].bytesperline < bpl) {
1334 + dev_err(dev, "%s: bpl mismatch on tdn_output\n",
1335 + __func__);
1336 + return -EINVAL;
1337 + }
1338 + if (fmt->fmt.pix_mp.plane_fmt[0].sizeimage < size) {
1339 + dev_err(dev, "%s: size mismatch on tdn_output\n",
1340 + __func__);
1341 + return -EINVAL;
1342 + }
1343 + }
1344 +
1345 + fmt = &node_group->node[STITCH_OUTPUT_NODE].format;
1346 + if (bayer_enables & PISP_BE_BAYER_ENABLE_STITCH_OUTPUT) {
1347 + bpl = config->config.stitch_output_format.stride;
1348 + size = bpl * config->config.stitch_output_format.height;
1349 + if (fmt->fmt.pix_mp.plane_fmt[0].bytesperline < bpl) {
1350 + dev_err(dev, "%s: bpl mismatch on stitch_output\n",
1351 + __func__);
1352 + return -EINVAL;
1353 + }
1354 + if (fmt->fmt.pix_mp.plane_fmt[0].sizeimage < size) {
1355 + dev_err(dev, "%s: size mismatch on stitch_output\n",
1356 + __func__);
1357 + return -EINVAL;
1358 + }
1359 + }
1360 +
1361 + for (j = 0; j < PISP_BACK_END_NUM_OUTPUTS; j++) {
1362 + if (!(rgb_enables & PISP_BE_RGB_ENABLE_OUTPUT(j)))
1363 + continue;
1364 + if (config->config.output_format[j].image.format &
1365 + PISP_IMAGE_FORMAT_WALLPAPER_ROLL)
1366 + continue; /* TODO: Size checks for wallpaper formats */
1367 +
1368 + fmt = &node_group->node[OUTPUT0_NODE + j].format;
1369 + for (i = 0; i < fmt->fmt.pix_mp.num_planes; i++) {
1370 + bpl = !i ? config->config.output_format[j].image.stride
1371 + : config->config.output_format[j].image.stride2;
1372 + size = bpl * config->config.output_format[j].image.height;
1373 +
1374 + if (config->config.output_format[j].image.format &
1375 + PISP_IMAGE_FORMAT_SAMPLING_420)
1376 + size >>= 1;
1377 + if (fmt->fmt.pix_mp.plane_fmt[i].bytesperline < bpl) {
1378 + dev_err(dev, "%s: bpl mismatch on output %d\n",
1379 + __func__, j);
1380 + return -EINVAL;
1381 + }
1382 + if (fmt->fmt.pix_mp.plane_fmt[i].sizeimage < size) {
1383 + dev_err(dev, "%s: size mismatch on output\n",
1384 + __func__);
1385 + return -EINVAL;
1386 + }
1387 + }
1388 + }
1389 +
1390 + return 0;
1391 +}
1392 +
1393 +static int pispbe_node_queue_setup(struct vb2_queue *q, unsigned int *nbuffers,
1394 + unsigned int *nplanes, unsigned int sizes[],
1395 + struct device *alloc_devs[])
1396 +{
1397 + struct pispbe_node *node = vb2_get_drv_priv(q);
1398 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1399 +
1400 + *nplanes = 1;
1401 + if (NODE_IS_MPLANE(node)) {
1402 + unsigned int i;
1403 +
1404 + *nplanes = node->format.fmt.pix_mp.num_planes;
1405 + for (i = 0; i < *nplanes; i++) {
1406 + unsigned int size =
1407 + node->format.fmt.pix_mp.plane_fmt[i].sizeimage;
1408 + if (sizes[i] && sizes[i] < size) {
1409 + dev_err(pispbe->dev, "%s: size %u < %u\n",
1410 + __func__, sizes[i], size);
1411 + return -EINVAL;
1412 + }
1413 + sizes[i] = size;
1414 + }
1415 + } else if (NODE_IS_META(node)) {
1416 + sizes[0] = node->format.fmt.meta.buffersize;
1417 + /*
1418 + * Limit the config node buffer count to the number of internal
1419 + * buffers allocated.
1420 + */
1421 + if (node->id == CONFIG_NODE)
1422 + *nbuffers = min_t(unsigned int, *nbuffers,
1423 + PISP_BE_NUM_CONFIG_BUFFERS);
1424 + }
1425 +
1426 + dev_dbg(pispbe->dev,
1427 + "Image (or metadata) size %u, nbuffers %u for node %s\n",
1428 + sizes[0], *nbuffers, NODE_NAME(node));
1429 +
1430 + return 0;
1431 +}
1432 +
1433 +static int pispbe_node_buffer_prepare(struct vb2_buffer *vb)
1434 +{
1435 + struct pispbe_node *node = vb2_get_drv_priv(vb->vb2_queue);
1436 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1437 + unsigned long size = 0;
1438 + unsigned int num_planes = NODE_IS_MPLANE(node) ?
1439 + node->format.fmt.pix_mp.num_planes : 1;
1440 + unsigned int i;
1441 +
1442 + for (i = 0; i < num_planes; i++) {
1443 + size = NODE_IS_MPLANE(node)
1444 + ? node->format.fmt.pix_mp.plane_fmt[i].sizeimage
1445 + : node->format.fmt.meta.buffersize;
1446 +
1447 + if (vb2_plane_size(vb, i) < size) {
1448 + dev_err(pispbe->dev,
1449 + "data will not fit into plane %d (%lu < %lu)\n",
1450 + i, vb2_plane_size(vb, i), size);
1451 + return -EINVAL;
1452 + }
1453 +
1454 + vb2_set_plane_payload(vb, i, size);
1455 + }
1456 +
1457 + if (node->id == CONFIG_NODE) {
1458 + void *dst = &node->node_group->config[vb->index];
1459 + void *src = vb2_plane_vaddr(vb, 0);
1460 +
1461 + memcpy(dst, src, sizeof(struct pisp_be_tiles_config));
1462 + return pisp_be_validate_config(node->node_group, dst);
1463 + }
1464 +
1465 + return 0;
1466 +}
1467 +
1468 +static void pispbe_node_buffer_queue(struct vb2_buffer *buf)
1469 +{
1470 + struct vb2_v4l2_buffer *vbuf =
1471 + container_of(buf, struct vb2_v4l2_buffer, vb2_buf);
1472 + struct pispbe_buffer *buffer =
1473 + container_of(vbuf, struct pispbe_buffer, vb);
1474 + struct pispbe_node *node = vb2_get_drv_priv(buf->vb2_queue);
1475 + struct pispbe_node_group *node_group = node->node_group;
1476 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1477 + unsigned long flags;
1478 +
1479 + dev_dbg(pispbe->dev, "%s: for node %s\n", __func__, NODE_NAME(node));
1480 + spin_lock_irqsave(&node->ready_lock, flags);
1481 + list_add_tail(&buffer->ready_list, &node->ready_queue);
1482 + spin_unlock_irqrestore(&node->ready_lock, flags);
1483 +
1484 + /*
1485 + * Every time we add a buffer, check if there's now some work for the hw
1486 + * to do, but only for this client.
1487 + */
1488 + pispbe_schedule_one(node_group);
1489 +}
1490 +
1491 +static int pispbe_node_start_streaming(struct vb2_queue *q, unsigned int count)
1492 +{
1493 + unsigned long flags;
1494 + struct pispbe_node *node = vb2_get_drv_priv(q);
1495 + struct pispbe_node_group *node_group = node->node_group;
1496 + struct pispbe_dev *pispbe = node_group->pispbe;
1497 + int ret;
1498 +
1499 + ret = pm_runtime_resume_and_get(pispbe->dev);
1500 + if (ret < 0)
1501 + return ret;
1502 +
1503 + spin_lock_irqsave(&pispbe->hw_lock, flags);
1504 + node->node_group->streaming_map |= BIT(node->id);
1505 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1506 +
1507 + dev_dbg(pispbe->dev, "%s: for node %s (count %u)\n",
1508 + __func__, NODE_NAME(node), count);
1509 + dev_dbg(pispbe->dev, "Nodes streaming for this group now 0x%x\n",
1510 + node->node_group->streaming_map);
1511 +
1512 + /* Maybe we're ready to run. */
1513 + pispbe_schedule_one(node_group);
1514 +
1515 + return 0;
1516 +}
1517 +
1518 +static void pispbe_node_stop_streaming(struct vb2_queue *q)
1519 +{
1520 + struct pispbe_node *node = vb2_get_drv_priv(q);
1521 + struct pispbe_node_group *node_group = node->node_group;
1522 + struct pispbe_dev *pispbe = node_group->pispbe;
1523 + struct pispbe_buffer *buf;
1524 + unsigned long flags;
1525 +
1526 + /*
1527 + * Now this is a bit awkward. In a simple M2M device we could just wait
1528 + * for all queued jobs to complete, but here there's a risk that a
1529 + * partial set of buffers was queued and cannot be run. For now, just
1530 + * cancel all buffers stuck in the "ready queue", then wait for any
1531 + * running job.
1532 + * XXX This may return buffers out of order.
1533 + */
1534 + dev_dbg(pispbe->dev, "%s: for node %s\n", __func__, NODE_NAME(node));
1535 + spin_lock_irqsave(&pispbe->hw_lock, flags);
1536 + do {
1537 + unsigned long flags1;
1538 +
1539 + spin_lock_irqsave(&node->ready_lock, flags1);
1540 + buf = list_first_entry_or_null(&node->ready_queue,
1541 + struct pispbe_buffer,
1542 + ready_list);
1543 + if (buf) {
1544 + list_del(&buf->ready_list);
1545 + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1546 + }
1547 + spin_unlock_irqrestore(&node->ready_lock, flags1);
1548 + } while (buf);
1549 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1550 +
1551 + vb2_wait_for_all_buffers(&node->queue);
1552 +
1553 + spin_lock_irqsave(&pispbe->hw_lock, flags);
1554 + node_group->streaming_map &= ~BIT(node->id);
1555 + spin_unlock_irqrestore(&pispbe->hw_lock, flags);
1556 +
1557 + pm_runtime_mark_last_busy(pispbe->dev);
1558 + pm_runtime_put_autosuspend(pispbe->dev);
1559 +
1560 + dev_dbg(pispbe->dev, "Nodes streaming for this group now 0x%x\n",
1561 + node_group->streaming_map);
1562 +}
1563 +
1564 +static const struct vb2_ops pispbe_node_queue_ops = {
1565 + .queue_setup = pispbe_node_queue_setup,
1566 + .buf_prepare = pispbe_node_buffer_prepare,
1567 + .buf_queue = pispbe_node_buffer_queue,
1568 + .start_streaming = pispbe_node_start_streaming,
1569 + .stop_streaming = pispbe_node_stop_streaming,
1570 +};
1571 +
1572 +static const struct v4l2_file_operations pispbe_fops = {
1573 + .owner = THIS_MODULE,
1574 + .open = v4l2_fh_open,
1575 + .release = vb2_fop_release,
1576 + .poll = vb2_fop_poll,
1577 + .unlocked_ioctl = video_ioctl2,
1578 + .mmap = vb2_fop_mmap
1579 +};
1580 +
1581 +static int pispbe_node_querycap(struct file *file, void *priv,
1582 + struct v4l2_capability *cap)
1583 +{
1584 + struct pispbe_node *node = video_drvdata(file);
1585 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1586 +
1587 + strscpy(cap->driver, PISPBE_NAME, sizeof(cap->driver));
1588 + strscpy(cap->card, PISPBE_NAME, sizeof(cap->card));
1589 + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1590 + dev_name(pispbe->dev));
1591 +
1592 + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1593 + V4L2_CAP_VIDEO_OUTPUT_MPLANE |
1594 + V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS |
1595 + V4L2_CAP_META_OUTPUT | V4L2_CAP_META_CAPTURE;
1596 + cap->device_caps = node->vfd.device_caps;
1597 +
1598 + dev_dbg(pispbe->dev, "Caps for node %s: %x and %x (dev %x)\n",
1599 + NODE_NAME(node), cap->capabilities, cap->device_caps,
1600 + node->vfd.device_caps);
1601 + return 0;
1602 +}
1603 +
1604 +static int pispbe_node_g_fmt_vid_cap(struct file *file, void *priv,
1605 + struct v4l2_format *f)
1606 +{
1607 + struct pispbe_node *node = video_drvdata(file);
1608 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1609 +
1610 + if (!NODE_IS_CAPTURE(node) || NODE_IS_META(node)) {
1611 + dev_err(pispbe->dev,
1612 + "Cannot get capture fmt for output node %s\n",
1613 + NODE_NAME(node));
1614 + return -EINVAL;
1615 + }
1616 + *f = node->format;
1617 + dev_dbg(pispbe->dev, "Get capture format for node %s\n",
1618 + NODE_NAME(node));
1619 + return 0;
1620 +}
1621 +
1622 +static int pispbe_node_g_fmt_vid_out(struct file *file, void *priv,
1623 + struct v4l2_format *f)
1624 +{
1625 + struct pispbe_node *node = video_drvdata(file);
1626 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1627 +
1628 + if (NODE_IS_CAPTURE(node) || NODE_IS_META(node)) {
1629 + dev_err(pispbe->dev,
1630 + "Cannot get capture fmt for output node %s\n",
1631 + NODE_NAME(node));
1632 + return -EINVAL;
1633 + }
1634 + *f = node->format;
1635 + dev_dbg(pispbe->dev, "Get output format for node %s\n",
1636 + NODE_NAME(node));
1637 + return 0;
1638 +}
1639 +
1640 +static int pispbe_node_g_fmt_meta_out(struct file *file, void *priv,
1641 + struct v4l2_format *f)
1642 +{
1643 + struct pispbe_node *node = video_drvdata(file);
1644 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1645 +
1646 + if (!NODE_IS_META(node) || NODE_IS_CAPTURE(node)) {
1647 + dev_err(pispbe->dev,
1648 + "Cannot get capture fmt for meta output node %s\n",
1649 + NODE_NAME(node));
1650 + return -EINVAL;
1651 + }
1652 + *f = node->format;
1653 + dev_dbg(pispbe->dev, "Get output format for meta node %s\n",
1654 + NODE_NAME(node));
1655 + return 0;
1656 +}
1657 +
1658 +static int pispbe_node_g_fmt_meta_cap(struct file *file, void *priv,
1659 + struct v4l2_format *f)
1660 +{
1661 + struct pispbe_node *node = video_drvdata(file);
1662 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1663 +
1664 + if (!NODE_IS_META(node) || NODE_IS_OUTPUT(node)) {
1665 + dev_err(pispbe->dev,
1666 + "Cannot get capture fmt for meta output node %s\n",
1667 + NODE_NAME(node));
1668 + return -EINVAL;
1669 + }
1670 + *f = node->format;
1671 + dev_dbg(pispbe->dev, "Get output format for meta node %s\n",
1672 + NODE_NAME(node));
1673 + return 0;
1674 +}
1675 +
1676 +static int verify_be_pix_format(const struct v4l2_format *f,
1677 + struct pispbe_node *node)
1678 +{
1679 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1680 + unsigned int nplanes = f->fmt.pix_mp.num_planes;
1681 + unsigned int i;
1682 +
1683 + if (f->fmt.pix_mp.width == 0 || f->fmt.pix_mp.height == 0) {
1684 + dev_err(pispbe->dev, "Details incorrect for output node %s\n",
1685 + NODE_NAME(node));
1686 + return -EINVAL;
1687 + }
1688 +
1689 + if (nplanes == 0 || nplanes > MAX_PLANES) {
1690 + dev_err(pispbe->dev,
1691 + "Bad number of planes for output node %s, req =%d\n",
1692 + NODE_NAME(node), nplanes);
1693 + return -EINVAL;
1694 + }
1695 +
1696 + for (i = 0; i < nplanes; i++) {
1697 + const struct v4l2_plane_pix_format *p;
1698 +
1699 + p = &f->fmt.pix_mp.plane_fmt[i];
1700 + if (p->bytesperline == 0 || p->sizeimage == 0) {
1701 + dev_err(pispbe->dev,
1702 + "Invalid plane %d for output node %s\n",
1703 + i, NODE_NAME(node));
1704 + return -EINVAL;
1705 + }
1706 + }
1707 +
1708 + return 0;
1709 +}
1710 +
1711 +static const struct pisp_be_format *find_format(unsigned int fourcc)
1712 +{
1713 + const struct pisp_be_format *fmt;
1714 + unsigned int i;
1715 +
1716 + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
1717 + fmt = &supported_formats[i];
1718 + if (fmt->fourcc == fourcc)
1719 + return fmt;
1720 + }
1721 +
1722 + return NULL;
1723 +}
1724 +
1725 +static void set_plane_params(struct v4l2_format *f,
1726 + const struct pisp_be_format *fmt)
1727 +{
1728 + unsigned int nplanes = f->fmt.pix_mp.num_planes;
1729 + unsigned int total_plane_factor = 0;
1730 + unsigned int i;
1731 +
1732 + for (i = 0; i < MAX_PLANES; i++)
1733 + total_plane_factor += fmt->plane_factor[i];
1734 +
1735 + for (i = 0; i < nplanes; i++) {
1736 + struct v4l2_plane_pix_format *p = &f->fmt.pix_mp.plane_fmt[i];
1737 + unsigned int bpl, plane_size;
1738 +
1739 + bpl = (f->fmt.pix_mp.width * fmt->bit_depth) >> 3;
1740 + bpl = ALIGN(max(p->bytesperline, bpl), fmt->align);
1741 +
1742 + plane_size = bpl * f->fmt.pix_mp.height *
1743 + (nplanes > 1 ? fmt->plane_factor[i] : total_plane_factor);
1744 + /*
1745 + * The shift is to divide out the plane_factor fixed point
1746 + * scaling of 8.
1747 + */
1748 + plane_size = max(p->sizeimage, plane_size >> 3);
1749 +
1750 + p->bytesperline = bpl;
1751 + p->sizeimage = plane_size;
1752 + }
1753 +}
1754 +
1755 +static int try_format(struct v4l2_format *f, struct pispbe_node *node)
1756 +{
1757 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1758 + const struct pisp_be_format *fmt;
1759 + unsigned int i;
1760 + bool is_rgb;
1761 + u32 pixfmt = f->fmt.pix_mp.pixelformat;
1762 +
1763 + dev_dbg(pispbe->dev,
1764 + "%s: [%s] req %ux%u " V4L2_FOURCC_CONV ", planes %d\n",
1765 + __func__, NODE_NAME(node), f->fmt.pix_mp.width,
1766 + f->fmt.pix_mp.height, V4L2_FOURCC_CONV_ARGS(pixfmt),
1767 + f->fmt.pix_mp.num_planes);
1768 +
1769 + if (pixfmt == V4L2_PIX_FMT_RPI_BE)
1770 + return verify_be_pix_format(f, node);
1771 +
1772 + fmt = find_format(pixfmt);
1773 + if (!fmt)
1774 + fmt = find_format(V4L2_PIX_FMT_YUV420M);
1775 +
1776 + f->fmt.pix_mp.pixelformat = fmt->fourcc;
1777 + f->fmt.pix_mp.num_planes = fmt->num_planes;
1778 + f->fmt.pix_mp.field = V4L2_FIELD_NONE;
1779 + f->fmt.pix_mp.width = max(min(f->fmt.pix_mp.width, 65536u),
1780 + PISP_BACK_END_MIN_TILE_WIDTH);
1781 + f->fmt.pix_mp.height = max(min(f->fmt.pix_mp.height, 65536u),
1782 + PISP_BACK_END_MIN_TILE_HEIGHT);
1783 +
1784 + /*
1785 + * Fill in the actual colour space when the requested one was
1786 + * not supported. This also catches the case when the "default"
1787 + * colour space was requested (as that's never in the mask).
1788 + */
1789 + if (!(V4L2_COLORSPACE_MASK(f->fmt.pix_mp.colorspace) & fmt->colorspace_mask))
1790 + f->fmt.pix_mp.colorspace = fmt->colorspace_default;
1791 +
1792 + /* In all cases, we only support the defaults for these: */
1793 + f->fmt.pix_mp.ycbcr_enc =
1794 + V4L2_MAP_YCBCR_ENC_DEFAULT(f->fmt.pix_mp.colorspace);
1795 + f->fmt.pix_mp.xfer_func =
1796 + V4L2_MAP_XFER_FUNC_DEFAULT(f->fmt.pix_mp.colorspace);
1797 +
1798 + is_rgb = f->fmt.pix_mp.colorspace == V4L2_COLORSPACE_SRGB;
1799 + f->fmt.pix_mp.quantization =
1800 + V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb, f->fmt.pix_mp.colorspace,
1801 + f->fmt.pix_mp.ycbcr_enc);
1802 +
1803 + /* Set plane size and bytes/line for each plane. */
1804 + set_plane_params(f, fmt);
1805 +
1806 + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
1807 + dev_dbg(pispbe->dev,
1808 + "%s: [%s] calc plane %d, %ux%u, depth %u, bpl %u size %u\n",
1809 + __func__, NODE_NAME(node), i, f->fmt.pix_mp.width,
1810 + f->fmt.pix_mp.height, fmt->bit_depth,
1811 + f->fmt.pix_mp.plane_fmt[i].bytesperline,
1812 + f->fmt.pix_mp.plane_fmt[i].sizeimage);
1813 + }
1814 +
1815 + return 0;
1816 +}
1817 +
1818 +static int pispbe_node_try_fmt_vid_cap(struct file *file, void *priv,
1819 + struct v4l2_format *f)
1820 +{
1821 + struct pispbe_node *node = video_drvdata(file);
1822 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1823 + int ret;
1824 +
1825 + if (!NODE_IS_CAPTURE(node) || NODE_IS_META(node)) {
1826 + dev_err(pispbe->dev,
1827 + "Cannot set capture fmt for output node %s\n",
1828 + NODE_NAME(node));
1829 + return -EINVAL;
1830 + }
1831 +
1832 + ret = try_format(f, node);
1833 + if (ret < 0)
1834 + return ret;
1835 +
1836 + return 0;
1837 +}
1838 +
1839 +static int pispbe_node_try_fmt_vid_out(struct file *file, void *priv,
1840 + struct v4l2_format *f)
1841 +{
1842 + struct pispbe_node *node = video_drvdata(file);
1843 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1844 + int ret;
1845 +
1846 + if (!NODE_IS_OUTPUT(node) || NODE_IS_META(node)) {
1847 + dev_err(pispbe->dev,
1848 + "Cannot set capture fmt for output node %s\n",
1849 + NODE_NAME(node));
1850 + return -EINVAL;
1851 + }
1852 +
1853 + ret = try_format(f, node);
1854 + if (ret < 0)
1855 + return ret;
1856 +
1857 + return 0;
1858 +}
1859 +
1860 +static int pispbe_node_try_fmt_meta_out(struct file *file, void *priv,
1861 + struct v4l2_format *f)
1862 +{
1863 + struct pispbe_node *node = video_drvdata(file);
1864 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1865 +
1866 + if (!NODE_IS_META(node) || NODE_IS_CAPTURE(node)) {
1867 + dev_err(pispbe->dev,
1868 + "Cannot set capture fmt for meta output node %s\n",
1869 + NODE_NAME(node));
1870 + return -EINVAL;
1871 + }
1872 +
1873 + f->fmt.meta.dataformat = V4L2_META_FMT_RPI_BE_CFG;
1874 + f->fmt.meta.buffersize = sizeof(struct pisp_be_tiles_config);
1875 +
1876 + return 0;
1877 +}
1878 +
1879 +static int pispbe_node_try_fmt_meta_cap(struct file *file, void *priv,
1880 + struct v4l2_format *f)
1881 +{
1882 + struct pispbe_node *node = video_drvdata(file);
1883 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1884 +
1885 + if (!NODE_IS_META(node) || NODE_IS_OUTPUT(node)) {
1886 + dev_err(pispbe->dev,
1887 + "Cannot set capture fmt for meta output node %s\n",
1888 + NODE_NAME(node));
1889 + return -EINVAL;
1890 + }
1891 +
1892 + f->fmt.meta.dataformat = V4L2_PIX_FMT_RPI_BE;
1893 + if (!f->fmt.meta.buffersize)
1894 + f->fmt.meta.buffersize = BIT(20);
1895 +
1896 + return 0;
1897 +}
1898 +
1899 +static int pispbe_node_s_fmt_vid_cap(struct file *file, void *priv,
1900 + struct v4l2_format *f)
1901 +{
1902 + struct pispbe_node *node = video_drvdata(file);
1903 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1904 + int ret = pispbe_node_try_fmt_vid_cap(file, priv, f);
1905 +
1906 + if (ret < 0)
1907 + return ret;
1908 +
1909 + node->format = *f;
1910 + node->pisp_format = find_format(f->fmt.pix_mp.pixelformat);
1911 +
1912 + dev_dbg(pispbe->dev,
1913 + "Set capture format for node %s to " V4L2_FOURCC_CONV "\n",
1914 + NODE_NAME(node),
1915 + V4L2_FOURCC_CONV_ARGS(f->fmt.pix_mp.pixelformat));
1916 + return 0;
1917 +}
1918 +
1919 +static int pispbe_node_s_fmt_vid_out(struct file *file, void *priv,
1920 + struct v4l2_format *f)
1921 +{
1922 + struct pispbe_node *node = video_drvdata(file);
1923 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1924 + int ret = pispbe_node_try_fmt_vid_out(file, priv, f);
1925 +
1926 + if (ret < 0)
1927 + return ret;
1928 +
1929 + node->format = *f;
1930 + node->pisp_format = find_format(f->fmt.pix_mp.pixelformat);
1931 +
1932 + dev_dbg(pispbe->dev,
1933 + "Set output format for node %s to " V4L2_FOURCC_CONV "\n",
1934 + NODE_NAME(node),
1935 + V4L2_FOURCC_CONV_ARGS(f->fmt.pix_mp.pixelformat));
1936 + return 0;
1937 +}
1938 +
1939 +static int pispbe_node_s_fmt_meta_out(struct file *file, void *priv,
1940 + struct v4l2_format *f)
1941 +{
1942 + struct pispbe_node *node = video_drvdata(file);
1943 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1944 + int ret = pispbe_node_try_fmt_meta_out(file, priv, f);
1945 +
1946 + if (ret < 0)
1947 + return ret;
1948 +
1949 + node->format = *f;
1950 + node->pisp_format = &meta_out_supported_formats[0];
1951 +
1952 + dev_dbg(pispbe->dev,
1953 + "Set output format for meta node %s to " V4L2_FOURCC_CONV "\n",
1954 + NODE_NAME(node),
1955 + V4L2_FOURCC_CONV_ARGS(f->fmt.meta.dataformat));
1956 + return 0;
1957 +}
1958 +
1959 +static int pispbe_node_s_fmt_meta_cap(struct file *file, void *priv,
1960 + struct v4l2_format *f)
1961 +{
1962 + struct pispbe_node *node = video_drvdata(file);
1963 + struct pispbe_dev *pispbe = node->node_group->pispbe;
1964 + int ret = pispbe_node_try_fmt_meta_cap(file, priv, f);
1965 +
1966 + if (ret < 0)
1967 + return ret;
1968 +
1969 + node->format = *f;
1970 + node->pisp_format = find_format(f->fmt.meta.dataformat);
1971 +
1972 + dev_dbg(pispbe->dev,
1973 + "Set capture format for meta node %s to " V4L2_FOURCC_CONV "\n",
1974 + NODE_NAME(node),
1975 + V4L2_FOURCC_CONV_ARGS(f->fmt.meta.dataformat));
1976 + return 0;
1977 +}
1978 +
1979 +static int pispbe_node_enum_fmt(struct file *file, void *priv,
1980 + struct v4l2_fmtdesc *f)
1981 +{
1982 + struct pispbe_node *node = video_drvdata(file);
1983 +
1984 + if (f->type != node->queue.type)
1985 + return -EINVAL;
1986 +
1987 + if (NODE_IS_META(node)) {
1988 + if (f->index)
1989 + return -EINVAL;
1990 +
1991 + if (NODE_IS_OUTPUT(node))
1992 + f->pixelformat = V4L2_META_FMT_RPI_BE_CFG;
1993 + else
1994 + f->pixelformat = V4L2_PIX_FMT_RPI_BE;
1995 + f->flags = 0;
1996 + return 0;
1997 + }
1998 +
1999 + if (f->index >= ARRAY_SIZE(supported_formats))
2000 + return -EINVAL;
2001 +
2002 + f->pixelformat = supported_formats[f->index].fourcc;
2003 + f->flags = 0;
2004 +
2005 + return 0;
2006 +}
2007 +
2008 +static int pispbe_enum_framesizes(struct file *file, void *priv,
2009 + struct v4l2_frmsizeenum *fsize)
2010 +{
2011 + struct pispbe_node *node = video_drvdata(file);
2012 + struct pispbe_dev *pispbe = node->node_group->pispbe;
2013 +
2014 + if (NODE_IS_META(node) || fsize->index)
2015 + return -EINVAL;
2016 +
2017 + if (!find_format(fsize->pixel_format)) {
2018 + dev_err(pispbe->dev, "Invalid pixel code: %x\n",
2019 + fsize->pixel_format);
2020 + return -EINVAL;
2021 + }
2022 +
2023 + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
2024 + fsize->stepwise.min_width = 32;
2025 + fsize->stepwise.max_width = 65535;
2026 + fsize->stepwise.step_width = 2;
2027 +
2028 + fsize->stepwise.min_height = 32;
2029 + fsize->stepwise.max_height = 65535;
2030 + fsize->stepwise.step_height = 2;
2031 +
2032 + return 0;
2033 +}
2034 +
2035 +static int pispbe_node_streamon(struct file *file, void *priv,
2036 + enum v4l2_buf_type type)
2037 +{
2038 + struct pispbe_node *node = video_drvdata(file);
2039 + struct pispbe_dev *pispbe = node->node_group->pispbe;
2040 +
2041 + /* Do we need a node->stream_lock mutex? */
2042 +
2043 + dev_dbg(pispbe->dev, "Stream on for node %s\n", NODE_NAME(node));
2044 +
2045 + /* Do we care about the type? Each node has only one queue. */
2046 +
2047 + INIT_LIST_HEAD(&node->ready_queue);
2048 +
2049 + /* locking should be handled by the queue->lock? */
2050 + return vb2_streamon(&node->queue, type);
2051 +}
2052 +
2053 +static int pispbe_node_streamoff(struct file *file, void *priv,
2054 + enum v4l2_buf_type type)
2055 +{
2056 + struct pispbe_node *node = video_drvdata(file);
2057 +
2058 + return vb2_streamoff(&node->queue, type);
2059 +}
2060 +
2061 +static const struct v4l2_ioctl_ops pispbe_node_ioctl_ops = {
2062 + .vidioc_querycap = pispbe_node_querycap,
2063 + .vidioc_g_fmt_vid_cap_mplane = pispbe_node_g_fmt_vid_cap,
2064 + .vidioc_g_fmt_vid_out_mplane = pispbe_node_g_fmt_vid_out,
2065 + .vidioc_g_fmt_meta_out = pispbe_node_g_fmt_meta_out,
2066 + .vidioc_g_fmt_meta_cap = pispbe_node_g_fmt_meta_cap,
2067 + .vidioc_try_fmt_vid_cap_mplane = pispbe_node_try_fmt_vid_cap,
2068 + .vidioc_try_fmt_vid_out_mplane = pispbe_node_try_fmt_vid_out,
2069 + .vidioc_try_fmt_meta_out = pispbe_node_try_fmt_meta_out,
2070 + .vidioc_try_fmt_meta_cap = pispbe_node_try_fmt_meta_cap,
2071 + .vidioc_s_fmt_vid_cap_mplane = pispbe_node_s_fmt_vid_cap,
2072 + .vidioc_s_fmt_vid_out_mplane = pispbe_node_s_fmt_vid_out,
2073 + .vidioc_s_fmt_meta_out = pispbe_node_s_fmt_meta_out,
2074 + .vidioc_s_fmt_meta_cap = pispbe_node_s_fmt_meta_cap,
2075 + .vidioc_enum_fmt_vid_cap = pispbe_node_enum_fmt,
2076 + .vidioc_enum_fmt_vid_out = pispbe_node_enum_fmt,
2077 + .vidioc_enum_fmt_meta_cap = pispbe_node_enum_fmt,
2078 + .vidioc_enum_fmt_meta_out = pispbe_node_enum_fmt,
2079 + .vidioc_enum_framesizes = pispbe_enum_framesizes,
2080 + .vidioc_create_bufs = vb2_ioctl_create_bufs,
2081 + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
2082 + .vidioc_querybuf = vb2_ioctl_querybuf,
2083 + .vidioc_qbuf = vb2_ioctl_qbuf,
2084 + .vidioc_dqbuf = vb2_ioctl_dqbuf,
2085 + .vidioc_expbuf = vb2_ioctl_expbuf,
2086 + .vidioc_reqbufs = vb2_ioctl_reqbufs,
2087 + .vidioc_streamon = pispbe_node_streamon,
2088 + .vidioc_streamoff = pispbe_node_streamoff,
2089 +};
2090 +
2091 +static const struct video_device pispbe_videodev = {
2092 + .name = PISPBE_NAME,
2093 + .vfl_dir = VFL_DIR_M2M, /* gets overwritten */
2094 + .fops = &pispbe_fops,
2095 + .ioctl_ops = &pispbe_node_ioctl_ops,
2096 + .minor = -1,
2097 + .release = video_device_release_empty,
2098 +};
2099 +
2100 +static void node_set_default_format(struct pispbe_node *node)
2101 +{
2102 + if (NODE_IS_META(node) && NODE_IS_OUTPUT(node)) {
2103 + /* Config node */
2104 + struct v4l2_format *f = &node->format;
2105 +
2106 + f->fmt.meta.dataformat = V4L2_META_FMT_RPI_BE_CFG;
2107 + f->fmt.meta.buffersize = sizeof(struct pisp_be_tiles_config);
2108 + f->type = node->buf_type;
2109 + } else if (NODE_IS_META(node) && NODE_IS_CAPTURE(node)) {
2110 + /* HOG output node */
2111 + struct v4l2_format *f = &node->format;
2112 +
2113 + f->fmt.meta.dataformat = V4L2_PIX_FMT_RPI_BE;
2114 + f->fmt.meta.buffersize = BIT(20);
2115 + f->type = node->buf_type;
2116 + } else {
2117 + struct v4l2_format f = {0};
2118 +
2119 + f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_YUV420M;
2120 + f.fmt.pix_mp.width = 1920;
2121 + f.fmt.pix_mp.height = 1080;
2122 + f.type = node->buf_type;
2123 + try_format(&f, node);
2124 + node->format = f;
2125 + }
2126 +
2127 + node->pisp_format = find_format(node->format.fmt.pix_mp.pixelformat);
2128 +}
2129 +
2130 +/*
2131 + * Initialise a struct pispbe_node and register it as /dev/video<N>
2132 + * to represent one of the PiSP Back End's input or output streams.
2133 + */
2134 +static int
2135 +pispbe_init_node(struct pispbe_node_group *node_group, unsigned int id)
2136 +{
2137 + bool output = NODE_DESC_IS_OUTPUT(&node_desc[id]);
2138 + struct pispbe_node *node = &node_group->node[id];
2139 + struct pispbe_dev *pispbe = node_group->pispbe;
2140 + struct media_entity *entity = &node->vfd.entity;
2141 + struct video_device *vdev = &node->vfd;
2142 + struct vb2_queue *q = &node->queue;
2143 + int ret;
2144 +
2145 + node->id = id;
2146 + node->node_group = node_group;
2147 + node->buf_type = node_desc[id].buf_type;
2148 +
2149 + mutex_init(&node->node_lock);
2150 + mutex_init(&node->queue_lock);
2151 + INIT_LIST_HEAD(&node->ready_queue);
2152 + spin_lock_init(&node->ready_lock);
2153 +
2154 + node->format.type = node->buf_type;
2155 + node_set_default_format(node);
2156 +
2157 + q->type = node->buf_type;
2158 + q->io_modes = VB2_MMAP | VB2_DMABUF;
2159 + q->mem_ops = &vb2_dma_contig_memops;
2160 + q->drv_priv = node;
2161 + q->ops = &pispbe_node_queue_ops;
2162 + q->buf_struct_size = sizeof(struct pispbe_buffer);
2163 + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2164 + q->dev = node->node_group->pispbe->dev;
2165 + /* get V4L2 to handle node->queue locking */
2166 + q->lock = &node->queue_lock;
2167 +
2168 + ret = vb2_queue_init(q);
2169 + if (ret < 0) {
2170 + dev_err(pispbe->dev, "vb2_queue_init failed\n");
2171 + return ret;
2172 + }
2173 +
2174 + *vdev = pispbe_videodev; /* default initialization */
2175 + strscpy(vdev->name, node_desc[id].ent_name, sizeof(vdev->name));
2176 + vdev->v4l2_dev = &node_group->v4l2_dev;
2177 + vdev->vfl_dir = output ? VFL_DIR_TX : VFL_DIR_RX;
2178 + /* get V4L2 to serialise our ioctls */
2179 + vdev->lock = &node->node_lock;
2180 + vdev->queue = &node->queue;
2181 + vdev->device_caps = V4L2_CAP_STREAMING | node_desc[id].caps;
2182 +
2183 + node->pad.flags = output ? MEDIA_PAD_FL_SOURCE : MEDIA_PAD_FL_SINK;
2184 + ret = media_entity_pads_init(entity, 1, &node->pad);
2185 + if (ret) {
2186 + dev_err(pispbe->dev,
2187 + "Failed to register media pads for %s device node\n",
2188 + NODE_NAME(node));
2189 + goto err_unregister_queue;
2190 + }
2191 +
2192 + ret = video_register_device(vdev, VFL_TYPE_VIDEO,
2193 + PISPBE_VIDEO_NODE_OFFSET);
2194 + if (ret) {
2195 + dev_err(pispbe->dev,
2196 + "Failed to register video %s device node\n",
2197 + NODE_NAME(node));
2198 + goto err_unregister_queue;
2199 + }
2200 + video_set_drvdata(vdev, node);
2201 +
2202 + if (output)
2203 + ret = media_create_pad_link(entity, 0, &node_group->sd.entity,
2204 + id, MEDIA_LNK_FL_IMMUTABLE |
2205 + MEDIA_LNK_FL_ENABLED);
2206 + else
2207 + ret = media_create_pad_link(&node_group->sd.entity, id, entity,
2208 + 0, MEDIA_LNK_FL_IMMUTABLE |
2209 + MEDIA_LNK_FL_ENABLED);
2210 + if (ret)
2211 + goto err_unregister_video_dev;
2212 +
2213 + dev_info(pispbe->dev,
2214 + "%s device node registered as /dev/video%d\n",
2215 + NODE_NAME(node), node->vfd.num);
2216 + return 0;
2217 +
2218 +err_unregister_video_dev:
2219 + video_unregister_device(&node->vfd);
2220 +err_unregister_queue:
2221 + vb2_queue_release(&node->queue);
2222 + return ret;
2223 +}
2224 +
2225 +static const struct v4l2_subdev_pad_ops pispbe_pad_ops = {
2226 + .link_validate = v4l2_subdev_link_validate_default,
2227 +};
2228 +
2229 +static const struct v4l2_subdev_ops pispbe_sd_ops = {
2230 + .pad = &pispbe_pad_ops,
2231 +};
2232 +
2233 +static int pispbe_init_subdev(struct pispbe_node_group *node_group)
2234 +{
2235 + struct pispbe_dev *pispbe = node_group->pispbe;
2236 + struct v4l2_subdev *sd = &node_group->sd;
2237 + unsigned int i;
2238 + int ret;
2239 +
2240 + v4l2_subdev_init(sd, &pispbe_sd_ops);
2241 + sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
2242 + sd->owner = THIS_MODULE;
2243 + sd->dev = pispbe->dev;
2244 + strscpy(sd->name, PISPBE_NAME, sizeof(sd->name));
2245 +
2246 + for (i = 0; i < PISPBE_NUM_NODES; i++)
2247 + node_group->pad[i].flags =
2248 + NODE_DESC_IS_OUTPUT(&node_desc[i]) ?
2249 + MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
2250 +
2251 + ret = media_entity_pads_init(&sd->entity, PISPBE_NUM_NODES,
2252 + node_group->pad);
2253 + if (ret)
2254 + goto error;
2255 +
2256 + ret = v4l2_device_register_subdev(&node_group->v4l2_dev, sd);
2257 + if (ret)
2258 + goto error;
2259 +
2260 + return 0;
2261 +
2262 +error:
2263 + media_entity_cleanup(&sd->entity);
2264 + return ret;
2265 +}
2266 +
2267 +static int pispbe_init_group(struct pispbe_dev *pispbe, unsigned int id)
2268 +{
2269 + struct pispbe_node_group *node_group = &pispbe->node_group[id];
2270 + struct v4l2_device *v4l2_dev;
2271 + struct media_device *mdev;
2272 + unsigned int num_registered = 0;
2273 + int ret;
2274 +
2275 + node_group->id = id;
2276 + node_group->pispbe = pispbe;
2277 + node_group->streaming_map = 0;
2278 +
2279 + dev_info(pispbe->dev, "Register nodes for group %u\n", id);
2280 +
2281 + /* Register v4l2_device and media_device */
2282 + mdev = &node_group->mdev;
2283 + mdev->hw_revision = node_group->pispbe->hw_version;
2284 + mdev->dev = node_group->pispbe->dev;
2285 + strscpy(mdev->model, PISPBE_NAME, sizeof(mdev->model));
2286 + snprintf(mdev->bus_info, sizeof(mdev->bus_info),
2287 + "platform:%s", dev_name(node_group->pispbe->dev));
2288 + media_device_init(mdev);
2289 +
2290 + v4l2_dev = &node_group->v4l2_dev;
2291 + v4l2_dev->mdev = &node_group->mdev;
2292 + strscpy(v4l2_dev->name, PISPBE_NAME, sizeof(v4l2_dev->name));
2293 +
2294 + ret = v4l2_device_register(pispbe->dev, &node_group->v4l2_dev);
2295 + if (ret)
2296 + goto err_media_dev_cleanup;
2297 +
2298 + /* Register the PISPBE subdevice. */
2299 + ret = pispbe_init_subdev(node_group);
2300 + if (ret)
2301 + goto err_unregister_v4l2;
2302 +
2303 + /* Create device video nodes */
2304 + for (; num_registered < PISPBE_NUM_NODES; num_registered++) {
2305 + ret = pispbe_init_node(node_group, num_registered);
2306 + if (ret)
2307 + goto err_unregister_nodes;
2308 + }
2309 +
2310 + ret = media_device_register(mdev);
2311 + if (ret)
2312 + goto err_unregister_nodes;
2313 +
2314 + node_group->config =
2315 + dma_alloc_coherent(pispbe->dev,
2316 + sizeof(struct pisp_be_tiles_config) *
2317 + PISP_BE_NUM_CONFIG_BUFFERS,
2318 + &node_group->config_dma_addr, GFP_KERNEL);
2319 + if (!node_group->config) {
2320 + dev_err(pispbe->dev, "Unable to allocate cached config buffers.\n");
2321 + ret = -ENOMEM;
2322 + goto err_unregister_mdev;
2323 + }
2324 +
2325 + return 0;
2326 +
2327 +err_unregister_mdev:
2328 + media_device_unregister(mdev);
2329 +err_unregister_nodes:
2330 + while (num_registered-- > 0) {
2331 + video_unregister_device(&node_group->node[num_registered].vfd);
2332 + vb2_queue_release(&node_group->node[num_registered].queue);
2333 + }
2334 + v4l2_device_unregister_subdev(&node_group->sd);
2335 + media_entity_cleanup(&node_group->sd.entity);
2336 +err_unregister_v4l2:
2337 + v4l2_device_unregister(v4l2_dev);
2338 +err_media_dev_cleanup:
2339 + media_device_cleanup(mdev);
2340 + return ret;
2341 +}
2342 +
2343 +static void pispbe_destroy_node_group(struct pispbe_node_group *node_group)
2344 +{
2345 + struct pispbe_dev *pispbe = node_group->pispbe;
2346 + int i;
2347 +
2348 + if (node_group->config) {
2349 + dma_free_coherent(node_group->pispbe->dev,
2350 + sizeof(struct pisp_be_tiles_config) *
2351 + PISP_BE_NUM_CONFIG_BUFFERS,
2352 + node_group->config,
2353 + node_group->config_dma_addr);
2354 + }
2355 +
2356 + dev_info(pispbe->dev, "Unregister from media controller\n");
2357 +
2358 + v4l2_device_unregister_subdev(&node_group->sd);
2359 + media_entity_cleanup(&node_group->sd.entity);
2360 + media_device_unregister(&node_group->mdev);
2361 +
2362 + for (i = PISPBE_NUM_NODES - 1; i >= 0; i--) {
2363 + video_unregister_device(&node_group->node[i].vfd);
2364 + vb2_queue_release(&node_group->node[i].queue);
2365 + }
2366 +
2367 + media_device_cleanup(&node_group->mdev);
2368 + v4l2_device_unregister(&node_group->v4l2_dev);
2369 +}
2370 +
2371 +static int pispbe_runtime_suspend(struct device *dev)
2372 +{
2373 + struct pispbe_dev *pispbe = dev_get_drvdata(dev);
2374 +
2375 + clk_disable_unprepare(pispbe->clk);
2376 +
2377 + return 0;
2378 +}
2379 +
2380 +static int pispbe_runtime_resume(struct device *dev)
2381 +{
2382 + struct pispbe_dev *pispbe = dev_get_drvdata(dev);
2383 + int ret;
2384 +
2385 + ret = clk_prepare_enable(pispbe->clk);
2386 + if (ret) {
2387 + dev_err(dev, "Unable to enable clock\n");
2388 + return ret;
2389 + }
2390 +
2391 + dev_dbg(dev, "%s: Enabled clock, rate=%lu\n",
2392 + __func__, clk_get_rate(pispbe->clk));
2393 +
2394 + return 0;
2395 +}
2396 +
2397 +/*
2398 + * Probe the ISP-BE hardware block, as a single platform device.
2399 + * This will instantiate multiple "node groups" each with many device nodes.
2400 + */
2401 +static int pispbe_probe(struct platform_device *pdev)
2402 +{
2403 + unsigned int num_groups = 0;
2404 + struct pispbe_dev *pispbe;
2405 + int ret;
2406 +
2407 + pispbe = devm_kzalloc(&pdev->dev, sizeof(*pispbe), GFP_KERNEL);
2408 + if (!pispbe)
2409 + return -ENOMEM;
2410 +
2411 + dev_set_drvdata(&pdev->dev, pispbe);
2412 + pispbe->dev = &pdev->dev;
2413 + platform_set_drvdata(pdev, pispbe);
2414 +
2415 + pispbe->be_reg_base = devm_platform_ioremap_resource(pdev, 0);
2416 + if (IS_ERR(pispbe->be_reg_base)) {
2417 + dev_err(&pdev->dev, "Failed to get ISP-BE registers address\n");
2418 + return PTR_ERR(pispbe->be_reg_base);
2419 + }
2420 +
2421 + pispbe->irq = platform_get_irq(pdev, 0);
2422 + if (pispbe->irq <= 0) {
2423 + dev_err(&pdev->dev, "No IRQ resource\n");
2424 + return -EINVAL;
2425 + }
2426 +
2427 + ret = devm_request_irq(&pdev->dev, pispbe->irq, pispbe_isr, 0,
2428 + PISPBE_NAME, pispbe);
2429 + if (ret) {
2430 + dev_err(&pdev->dev, "Unable to request interrupt\n");
2431 + return ret;
2432 + }
2433 +
2434 + ret = dma_set_mask_and_coherent(pispbe->dev, DMA_BIT_MASK(36));
2435 + if (ret)
2436 + return ret;
2437 +
2438 + pispbe->clk = devm_clk_get(&pdev->dev, NULL);
2439 + if (IS_ERR(pispbe->clk))
2440 + return dev_err_probe(&pdev->dev, PTR_ERR(pispbe->clk),
2441 + "Failed to get clock");
2442 +
2443 + /* Hardware initialisation */
2444 + pm_runtime_set_autosuspend_delay(pispbe->dev, 200);
2445 + pm_runtime_use_autosuspend(pispbe->dev);
2446 + pm_runtime_enable(pispbe->dev);
2447 +
2448 + ret = pm_runtime_resume_and_get(pispbe->dev);
2449 + if (ret)
2450 + goto pm_runtime_disable_err;
2451 +
2452 + pispbe->hw_busy = 0;
2453 + spin_lock_init(&pispbe->hw_lock);
2454 + ret = hw_init(pispbe);
2455 + if (ret)
2456 + goto pm_runtime_put_err;
2457 +
2458 + /*
2459 + * Initialise and register devices for each node_group, including media
2460 + * device
2461 + */
2462 + for (num_groups = 0;
2463 + num_groups < PISPBE_NUM_NODE_GROUPS;
2464 + num_groups++) {
2465 + ret = pispbe_init_group(pispbe, num_groups);
2466 + if (ret)
2467 + goto disable_nodes_err;
2468 + }
2469 +
2470 + pm_runtime_mark_last_busy(pispbe->dev);
2471 + pm_runtime_put_autosuspend(pispbe->dev);
2472 +
2473 + return 0;
2474 +
2475 +disable_nodes_err:
2476 + while (num_groups-- > 0)
2477 + pispbe_destroy_node_group(&pispbe->node_group[num_groups]);
2478 +pm_runtime_put_err:
2479 + pm_runtime_put(pispbe->dev);
2480 +pm_runtime_disable_err:
2481 + pm_runtime_dont_use_autosuspend(pispbe->dev);
2482 + pm_runtime_disable(pispbe->dev);
2483 +
2484 + dev_err(&pdev->dev, "%s: returning %d", __func__, ret);
2485 +
2486 + return ret;
2487 +}
2488 +
2489 +static int pispbe_remove(struct platform_device *pdev)
2490 +{
2491 + struct pispbe_dev *pispbe = platform_get_drvdata(pdev);
2492 + int i;
2493 +
2494 + for (i = PISPBE_NUM_NODE_GROUPS - 1; i >= 0; i--)
2495 + pispbe_destroy_node_group(&pispbe->node_group[i]);
2496 +
2497 + pm_runtime_dont_use_autosuspend(pispbe->dev);
2498 + pm_runtime_disable(pispbe->dev);
2499 +
2500 + return 0;
2501 +}
2502 +
2503 +static const struct dev_pm_ops pispbe_pm_ops = {
2504 + SET_RUNTIME_PM_OPS(pispbe_runtime_suspend, pispbe_runtime_resume, NULL)
2505 +};
2506 +
2507 +static const struct of_device_id pispbe_of_match[] = {
2508 + {
2509 + .compatible = "raspberrypi,pispbe",
2510 + },
2511 + { /* sentinel */ },
2512 +};
2513 +MODULE_DEVICE_TABLE(of, pispbe_of_match);
2514 +
2515 +static struct platform_driver pispbe_pdrv = {
2516 + .probe = pispbe_probe,
2517 + .remove = pispbe_remove,
2518 + .driver = {
2519 + .name = PISPBE_NAME,
2520 + .of_match_table = pispbe_of_match,
2521 + .pm = &pispbe_pm_ops,
2522 + },
2523 +};
2524 +
2525 +module_platform_driver(pispbe_pdrv);
2526 --- /dev/null
2527 +++ b/drivers/media/platform/raspberrypi/pisp_be/pisp_be_config.h
2528 @@ -0,0 +1,533 @@
2529 +/* SPDX-License-Identifier: GPL-2.0-only */
2530 +/*
2531 + * PiSP Back End configuration definitions.
2532 + *
2533 + * Copyright (C) 2021 - Raspberry Pi Ltd
2534 + *
2535 + */
2536 +#ifndef _PISP_BE_CONFIG_H_
2537 +#define _PISP_BE_CONFIG_H_
2538 +
2539 +#include <linux/types.h>
2540 +
2541 +#include <media/raspberrypi/pisp_common.h>
2542 +
2543 +/* byte alignment for inputs */
2544 +#define PISP_BACK_END_INPUT_ALIGN 4u
2545 +/* alignment for compressed inputs */
2546 +#define PISP_BACK_END_COMPRESSED_ALIGN 8u
2547 +/* minimum required byte alignment for outputs */
2548 +#define PISP_BACK_END_OUTPUT_MIN_ALIGN 16u
2549 +/* preferred byte alignment for outputs */
2550 +#define PISP_BACK_END_OUTPUT_MAX_ALIGN 64u
2551 +
2552 +/* minimum allowed tile width anywhere in the pipeline */
2553 +#define PISP_BACK_END_MIN_TILE_WIDTH 16u
2554 +/* minimum allowed tile width anywhere in the pipeline */
2555 +#define PISP_BACK_END_MIN_TILE_HEIGHT 16u
2556 +
2557 +#define PISP_BACK_END_NUM_OUTPUTS 2
2558 +#define PISP_BACK_END_HOG_OUTPUT 1
2559 +
2560 +#define PISP_BACK_END_NUM_TILES 64
2561 +
2562 +enum pisp_be_bayer_enable {
2563 + PISP_BE_BAYER_ENABLE_INPUT = 0x000001,
2564 + PISP_BE_BAYER_ENABLE_DECOMPRESS = 0x000002,
2565 + PISP_BE_BAYER_ENABLE_DPC = 0x000004,
2566 + PISP_BE_BAYER_ENABLE_GEQ = 0x000008,
2567 + PISP_BE_BAYER_ENABLE_TDN_INPUT = 0x000010,
2568 + PISP_BE_BAYER_ENABLE_TDN_DECOMPRESS = 0x000020,
2569 + PISP_BE_BAYER_ENABLE_TDN = 0x000040,
2570 + PISP_BE_BAYER_ENABLE_TDN_COMPRESS = 0x000080,
2571 + PISP_BE_BAYER_ENABLE_TDN_OUTPUT = 0x000100,
2572 + PISP_BE_BAYER_ENABLE_SDN = 0x000200,
2573 + PISP_BE_BAYER_ENABLE_BLC = 0x000400,
2574 + PISP_BE_BAYER_ENABLE_STITCH_INPUT = 0x000800,
2575 + PISP_BE_BAYER_ENABLE_STITCH_DECOMPRESS = 0x001000,
2576 + PISP_BE_BAYER_ENABLE_STITCH = 0x002000,
2577 + PISP_BE_BAYER_ENABLE_STITCH_COMPRESS = 0x004000,
2578 + PISP_BE_BAYER_ENABLE_STITCH_OUTPUT = 0x008000,
2579 + PISP_BE_BAYER_ENABLE_WBG = 0x010000,
2580 + PISP_BE_BAYER_ENABLE_CDN = 0x020000,
2581 + PISP_BE_BAYER_ENABLE_LSC = 0x040000,
2582 + PISP_BE_BAYER_ENABLE_TONEMAP = 0x080000,
2583 + PISP_BE_BAYER_ENABLE_CAC = 0x100000,
2584 + PISP_BE_BAYER_ENABLE_DEBIN = 0x200000,
2585 + PISP_BE_BAYER_ENABLE_DEMOSAIC = 0x400000,
2586 +};
2587 +
2588 +enum pisp_be_rgb_enable {
2589 + PISP_BE_RGB_ENABLE_INPUT = 0x000001,
2590 + PISP_BE_RGB_ENABLE_CCM = 0x000002,
2591 + PISP_BE_RGB_ENABLE_SAT_CONTROL = 0x000004,
2592 + PISP_BE_RGB_ENABLE_YCBCR = 0x000008,
2593 + PISP_BE_RGB_ENABLE_FALSE_COLOUR = 0x000010,
2594 + PISP_BE_RGB_ENABLE_SHARPEN = 0x000020,
2595 + /* Preferred colours would occupy 0x000040 */
2596 + PISP_BE_RGB_ENABLE_YCBCR_INVERSE = 0x000080,
2597 + PISP_BE_RGB_ENABLE_GAMMA = 0x000100,
2598 + PISP_BE_RGB_ENABLE_CSC0 = 0x000200,
2599 + PISP_BE_RGB_ENABLE_CSC1 = 0x000400,
2600 + PISP_BE_RGB_ENABLE_DOWNSCALE0 = 0x001000,
2601 + PISP_BE_RGB_ENABLE_DOWNSCALE1 = 0x002000,
2602 + PISP_BE_RGB_ENABLE_RESAMPLE0 = 0x008000,
2603 + PISP_BE_RGB_ENABLE_RESAMPLE1 = 0x010000,
2604 + PISP_BE_RGB_ENABLE_OUTPUT0 = 0x040000,
2605 + PISP_BE_RGB_ENABLE_OUTPUT1 = 0x080000,
2606 + PISP_BE_RGB_ENABLE_HOG = 0x200000
2607 +};
2608 +
2609 +#define PISP_BE_RGB_ENABLE_CSC(i) (PISP_BE_RGB_ENABLE_CSC0 << (i))
2610 +#define PISP_BE_RGB_ENABLE_DOWNSCALE(i) (PISP_BE_RGB_ENABLE_DOWNSCALE0 << (i))
2611 +#define PISP_BE_RGB_ENABLE_RESAMPLE(i) (PISP_BE_RGB_ENABLE_RESAMPLE0 << (i))
2612 +#define PISP_BE_RGB_ENABLE_OUTPUT(i) (PISP_BE_RGB_ENABLE_OUTPUT0 << (i))
2613 +
2614 +/*
2615 + * We use the enable flags to show when blocks are "dirty", but we need some
2616 + * extra ones too.
2617 + */
2618 +enum pisp_be_dirty {
2619 + PISP_BE_DIRTY_GLOBAL = 0x0001,
2620 + PISP_BE_DIRTY_SH_FC_COMBINE = 0x0002,
2621 + PISP_BE_DIRTY_CROP = 0x0004
2622 +};
2623 +
2624 +struct pisp_be_global_config {
2625 + u32 bayer_enables;
2626 + u32 rgb_enables;
2627 + u8 bayer_order;
2628 + u8 pad[3];
2629 +};
2630 +
2631 +struct pisp_be_input_buffer_config {
2632 + /* low 32 bits followed by high 32 bits (for each of up to 3 planes) */
2633 + u32 addr[3][2];
2634 +};
2635 +
2636 +struct pisp_be_dpc_config {
2637 + u8 coeff_level;
2638 + u8 coeff_range;
2639 + u8 pad;
2640 +#define PISP_BE_DPC_FLAG_FOLDBACK 1
2641 + u8 flags;
2642 +};
2643 +
2644 +struct pisp_be_geq_config {
2645 + u16 offset;
2646 +#define PISP_BE_GEQ_SHARPER BIT(15)
2647 +#define PISP_BE_GEQ_SLOPE ((1 << 10) - 1)
2648 + /* top bit is the "sharper" flag, slope value is bottom 10 bits */
2649 + u16 slope_sharper;
2650 + u16 min;
2651 + u16 max;
2652 +};
2653 +
2654 +struct pisp_be_tdn_input_buffer_config {
2655 + /* low 32 bits followed by high 32 bits */
2656 + u32 addr[2];
2657 +};
2658 +
2659 +struct pisp_be_tdn_config {
2660 + u16 black_level;
2661 + u16 ratio;
2662 + u16 noise_constant;
2663 + u16 noise_slope;
2664 + u16 threshold;
2665 + u8 reset;
2666 + u8 pad;
2667 +};
2668 +
2669 +struct pisp_be_tdn_output_buffer_config {
2670 + /* low 32 bits followed by high 32 bits */
2671 + u32 addr[2];
2672 +};
2673 +
2674 +struct pisp_be_sdn_config {
2675 + u16 black_level;
2676 + u8 leakage;
2677 + u8 pad;
2678 + u16 noise_constant;
2679 + u16 noise_slope;
2680 + u16 noise_constant2;
2681 + u16 noise_slope2;
2682 +};
2683 +
2684 +struct pisp_be_stitch_input_buffer_config {
2685 + /* low 32 bits followed by high 32 bits */
2686 + u32 addr[2];
2687 +};
2688 +
2689 +#define PISP_BE_STITCH_STREAMING_LONG 0x8000
2690 +#define PISP_BE_STITCH_EXPOSURE_RATIO_MASK 0x7fff
2691 +
2692 +struct pisp_be_stitch_config {
2693 + u16 threshold_lo;
2694 + u8 threshold_diff_power;
2695 + u8 pad;
2696 +
2697 + /* top bit indicates whether streaming input is the long exposure */
2698 + u16 exposure_ratio;
2699 +
2700 + u8 motion_threshold_256;
2701 + u8 motion_threshold_recip;
2702 +};
2703 +
2704 +struct pisp_be_stitch_output_buffer_config {
2705 + /* low 32 bits followed by high 32 bits */
2706 + u32 addr[2];
2707 +};
2708 +
2709 +struct pisp_be_cdn_config {
2710 + u16 thresh;
2711 + u8 iir_strength;
2712 + u8 g_adjust;
2713 +};
2714 +
2715 +#define PISP_BE_LSC_LOG_GRID_SIZE 5
2716 +#define PISP_BE_LSC_GRID_SIZE (1 << PISP_BE_LSC_LOG_GRID_SIZE)
2717 +#define PISP_BE_LSC_STEP_PRECISION 18
2718 +
2719 +struct pisp_be_lsc_config {
2720 + /* (1<<18) / grid_cell_width */
2721 + u16 grid_step_x;
2722 + /* (1<<18) / grid_cell_height */
2723 + u16 grid_step_y;
2724 + /* RGB gains jointly encoded in 32 bits */
2725 + u32 lut_packed[PISP_BE_LSC_GRID_SIZE + 1]
2726 + [PISP_BE_LSC_GRID_SIZE + 1];
2727 +};
2728 +
2729 +struct pisp_be_lsc_extra {
2730 + u16 offset_x;
2731 + u16 offset_y;
2732 +};
2733 +
2734 +#define PISP_BE_CAC_LOG_GRID_SIZE 3
2735 +#define PISP_BE_CAC_GRID_SIZE (1 << PISP_BE_CAC_LOG_GRID_SIZE)
2736 +#define PISP_BE_CAC_STEP_PRECISION 20
2737 +
2738 +struct pisp_be_cac_config {
2739 + /* (1<<20) / grid_cell_width */
2740 + u16 grid_step_x;
2741 + /* (1<<20) / grid_cell_height */
2742 + u16 grid_step_y;
2743 + /* [gridy][gridx][rb][xy] */
2744 + s8 lut[PISP_BE_CAC_GRID_SIZE + 1][PISP_BE_CAC_GRID_SIZE + 1][2][2];
2745 +};
2746 +
2747 +struct pisp_be_cac_extra {
2748 + u16 offset_x;
2749 + u16 offset_y;
2750 +};
2751 +
2752 +#define PISP_BE_DEBIN_NUM_COEFFS 4
2753 +
2754 +struct pisp_be_debin_config {
2755 + s8 coeffs[PISP_BE_DEBIN_NUM_COEFFS];
2756 + s8 h_enable;
2757 + s8 v_enable;
2758 + s8 pad[2];
2759 +};
2760 +
2761 +#define PISP_BE_TONEMAP_LUT_SIZE 64
2762 +
2763 +struct pisp_be_tonemap_config {
2764 + u16 detail_constant;
2765 + u16 detail_slope;
2766 + u16 iir_strength;
2767 + u16 strength;
2768 + u32 lut[PISP_BE_TONEMAP_LUT_SIZE];
2769 +};
2770 +
2771 +struct pisp_be_demosaic_config {
2772 + u8 sharper;
2773 + u8 fc_mode;
2774 + u8 pad[2];
2775 +};
2776 +
2777 +struct pisp_be_ccm_config {
2778 + s16 coeffs[9];
2779 + u8 pad[2];
2780 + s32 offsets[3];
2781 +};
2782 +
2783 +struct pisp_be_sat_control_config {
2784 + u8 shift_r;
2785 + u8 shift_g;
2786 + u8 shift_b;
2787 + u8 pad;
2788 +};
2789 +
2790 +struct pisp_be_false_colour_config {
2791 + u8 distance;
2792 + u8 pad[3];
2793 +};
2794 +
2795 +#define PISP_BE_SHARPEN_SIZE 5
2796 +#define PISP_BE_SHARPEN_FUNC_NUM_POINTS 9
2797 +
2798 +struct pisp_be_sharpen_config {
2799 + s8 kernel0[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
2800 + s8 pad0[3];
2801 + s8 kernel1[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
2802 + s8 pad1[3];
2803 + s8 kernel2[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
2804 + s8 pad2[3];
2805 + s8 kernel3[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
2806 + s8 pad3[3];
2807 + s8 kernel4[PISP_BE_SHARPEN_SIZE * PISP_BE_SHARPEN_SIZE];
2808 + s8 pad4[3];
2809 + u16 threshold_offset0;
2810 + u16 threshold_slope0;
2811 + u16 scale0;
2812 + u16 pad5;
2813 + u16 threshold_offset1;
2814 + u16 threshold_slope1;
2815 + u16 scale1;
2816 + u16 pad6;
2817 + u16 threshold_offset2;
2818 + u16 threshold_slope2;
2819 + u16 scale2;
2820 + u16 pad7;
2821 + u16 threshold_offset3;
2822 + u16 threshold_slope3;
2823 + u16 scale3;
2824 + u16 pad8;
2825 + u16 threshold_offset4;
2826 + u16 threshold_slope4;
2827 + u16 scale4;
2828 + u16 pad9;
2829 + u16 positive_strength;
2830 + u16 positive_pre_limit;
2831 + u16 positive_func[PISP_BE_SHARPEN_FUNC_NUM_POINTS];
2832 + u16 positive_limit;
2833 + u16 negative_strength;
2834 + u16 negative_pre_limit;
2835 + u16 negative_func[PISP_BE_SHARPEN_FUNC_NUM_POINTS];
2836 + u16 negative_limit;
2837 + u8 enables;
2838 + u8 white;
2839 + u8 black;
2840 + u8 grey;
2841 +};
2842 +
2843 +struct pisp_be_sh_fc_combine_config {
2844 + u8 y_factor;
2845 + u8 c1_factor;
2846 + u8 c2_factor;
2847 + u8 pad;
2848 +};
2849 +
2850 +#define PISP_BE_GAMMA_LUT_SIZE 64
2851 +
2852 +struct pisp_be_gamma_config {
2853 + u32 lut[PISP_BE_GAMMA_LUT_SIZE];
2854 +};
2855 +
2856 +struct pisp_be_crop_config {
2857 + u16 offset_x, offset_y;
2858 + u16 width, height;
2859 +};
2860 +
2861 +#define PISP_BE_RESAMPLE_FILTER_SIZE 96
2862 +
2863 +struct pisp_be_resample_config {
2864 + u16 scale_factor_h, scale_factor_v;
2865 + s16 coef[PISP_BE_RESAMPLE_FILTER_SIZE];
2866 +};
2867 +
2868 +struct pisp_be_resample_extra {
2869 + u16 scaled_width;
2870 + u16 scaled_height;
2871 + s16 initial_phase_h[3];
2872 + s16 initial_phase_v[3];
2873 +};
2874 +
2875 +struct pisp_be_downscale_config {
2876 + u16 scale_factor_h;
2877 + u16 scale_factor_v;
2878 + u16 scale_recip_h;
2879 + u16 scale_recip_v;
2880 +};
2881 +
2882 +struct pisp_be_downscale_extra {
2883 + u16 scaled_width;
2884 + u16 scaled_height;
2885 +};
2886 +
2887 +struct pisp_be_hog_config {
2888 + u8 compute_signed;
2889 + u8 channel_mix[3];
2890 + u32 stride;
2891 +};
2892 +
2893 +struct pisp_be_axi_config {
2894 + u8 r_qos; /* Read QoS */
2895 + u8 r_cache_prot; /* Read { prot[2:0], cache[3:0] } */
2896 + u8 w_qos; /* Write QoS */
2897 + u8 w_cache_prot; /* Write { prot[2:0], cache[3:0] } */
2898 +};
2899 +
2900 +enum pisp_be_transform {
2901 + PISP_BE_TRANSFORM_NONE = 0x0,
2902 + PISP_BE_TRANSFORM_HFLIP = 0x1,
2903 + PISP_BE_TRANSFORM_VFLIP = 0x2,
2904 + PISP_BE_TRANSFORM_ROT180 =
2905 + (PISP_BE_TRANSFORM_HFLIP | PISP_BE_TRANSFORM_VFLIP)
2906 +};
2907 +
2908 +struct pisp_be_output_format_config {
2909 + struct pisp_image_format_config image;
2910 + u8 transform;
2911 + u8 pad[3];
2912 + u16 lo;
2913 + u16 hi;
2914 + u16 lo2;
2915 + u16 hi2;
2916 +};
2917 +
2918 +struct pisp_be_output_buffer_config {
2919 + /* low 32 bits followed by high 32 bits (for each of 3 planes) */
2920 + u32 addr[3][2];
2921 +};
2922 +
2923 +struct pisp_be_hog_buffer_config {
2924 + /* low 32 bits followed by high 32 bits */
2925 + u32 addr[2];
2926 +};
2927 +
2928 +struct pisp_be_config {
2929 + /* I/O configuration: */
2930 + struct pisp_be_input_buffer_config input_buffer;
2931 + struct pisp_be_tdn_input_buffer_config tdn_input_buffer;
2932 + struct pisp_be_stitch_input_buffer_config stitch_input_buffer;
2933 + struct pisp_be_tdn_output_buffer_config tdn_output_buffer;
2934 + struct pisp_be_stitch_output_buffer_config stitch_output_buffer;
2935 + struct pisp_be_output_buffer_config
2936 + output_buffer[PISP_BACK_END_NUM_OUTPUTS];
2937 + struct pisp_be_hog_buffer_config hog_buffer;
2938 + /* Processing configuration: */
2939 + struct pisp_be_global_config global;
2940 + struct pisp_image_format_config input_format;
2941 + struct pisp_decompress_config decompress;
2942 + struct pisp_be_dpc_config dpc;
2943 + struct pisp_be_geq_config geq;
2944 + struct pisp_image_format_config tdn_input_format;
2945 + struct pisp_decompress_config tdn_decompress;
2946 + struct pisp_be_tdn_config tdn;
2947 + struct pisp_compress_config tdn_compress;
2948 + struct pisp_image_format_config tdn_output_format;
2949 + struct pisp_be_sdn_config sdn;
2950 + struct pisp_bla_config blc;
2951 + struct pisp_compress_config stitch_compress;
2952 + struct pisp_image_format_config stitch_output_format;
2953 + struct pisp_image_format_config stitch_input_format;
2954 + struct pisp_decompress_config stitch_decompress;
2955 + struct pisp_be_stitch_config stitch;
2956 + struct pisp_be_lsc_config lsc;
2957 + struct pisp_wbg_config wbg;
2958 + struct pisp_be_cdn_config cdn;
2959 + struct pisp_be_cac_config cac;
2960 + struct pisp_be_debin_config debin;
2961 + struct pisp_be_tonemap_config tonemap;
2962 + struct pisp_be_demosaic_config demosaic;
2963 + struct pisp_be_ccm_config ccm;
2964 + struct pisp_be_sat_control_config sat_control;
2965 + struct pisp_be_ccm_config ycbcr;
2966 + struct pisp_be_sharpen_config sharpen;
2967 + struct pisp_be_false_colour_config false_colour;
2968 + struct pisp_be_sh_fc_combine_config sh_fc_combine;
2969 + struct pisp_be_ccm_config ycbcr_inverse;
2970 + struct pisp_be_gamma_config gamma;
2971 + struct pisp_be_ccm_config csc[PISP_BACK_END_NUM_OUTPUTS];
2972 + struct pisp_be_downscale_config downscale[PISP_BACK_END_NUM_OUTPUTS];
2973 + struct pisp_be_resample_config resample[PISP_BACK_END_NUM_OUTPUTS];
2974 + struct pisp_be_output_format_config
2975 + output_format[PISP_BACK_END_NUM_OUTPUTS];
2976 + struct pisp_be_hog_config hog;
2977 + struct pisp_be_axi_config axi;
2978 + /* Non-register fields: */
2979 + struct pisp_be_lsc_extra lsc_extra;
2980 + struct pisp_be_cac_extra cac_extra;
2981 + struct pisp_be_downscale_extra
2982 + downscale_extra[PISP_BACK_END_NUM_OUTPUTS];
2983 + struct pisp_be_resample_extra resample_extra[PISP_BACK_END_NUM_OUTPUTS];
2984 + struct pisp_be_crop_config crop;
2985 + struct pisp_image_format_config hog_format;
2986 + u32 dirty_flags_bayer; /* these use pisp_be_bayer_enable */
2987 + u32 dirty_flags_rgb; /* use pisp_be_rgb_enable */
2988 + u32 dirty_flags_extra; /* these use pisp_be_dirty_t */
2989 +};
2990 +
2991 +/*
2992 + * We also need a tile structure to describe the size of the tiles going
2993 + * through the pipeline.
2994 + */
2995 +
2996 +enum pisp_tile_edge {
2997 + PISP_LEFT_EDGE = (1 << 0),
2998 + PISP_RIGHT_EDGE = (1 << 1),
2999 + PISP_TOP_EDGE = (1 << 2),
3000 + PISP_BOTTOM_EDGE = (1 << 3)
3001 +};
3002 +
3003 +struct pisp_tile {
3004 + u8 edge; // enum pisp_tile_edge
3005 + u8 pad0[3];
3006 + // 4 bytes
3007 + u32 input_addr_offset;
3008 + u32 input_addr_offset2;
3009 + u16 input_offset_x;
3010 + u16 input_offset_y;
3011 + u16 input_width;
3012 + u16 input_height;
3013 + // 20 bytes
3014 + u32 tdn_input_addr_offset;
3015 + u32 tdn_output_addr_offset;
3016 + u32 stitch_input_addr_offset;
3017 + u32 stitch_output_addr_offset;
3018 + // 36 bytes
3019 + u32 lsc_grid_offset_x;
3020 + u32 lsc_grid_offset_y;
3021 + // 44 bytes
3022 + u32 cac_grid_offset_x;
3023 + u32 cac_grid_offset_y;
3024 + // 52 bytes
3025 + u16 crop_x_start[PISP_BACK_END_NUM_OUTPUTS];
3026 + u16 crop_x_end[PISP_BACK_END_NUM_OUTPUTS];
3027 + u16 crop_y_start[PISP_BACK_END_NUM_OUTPUTS];
3028 + u16 crop_y_end[PISP_BACK_END_NUM_OUTPUTS];
3029 + // 68 bytes
3030 + /* Ordering is planes then branches */
3031 + u16 downscale_phase_x[3 * PISP_BACK_END_NUM_OUTPUTS];
3032 + u16 downscale_phase_y[3 * PISP_BACK_END_NUM_OUTPUTS];
3033 + // 92 bytes
3034 + u16 resample_in_width[PISP_BACK_END_NUM_OUTPUTS];
3035 + u16 resample_in_height[PISP_BACK_END_NUM_OUTPUTS];
3036 + // 100 bytes
3037 + /* Ordering is planes then branches */
3038 + u16 resample_phase_x[3 * PISP_BACK_END_NUM_OUTPUTS];
3039 + u16 resample_phase_y[3 * PISP_BACK_END_NUM_OUTPUTS];
3040 + // 124 bytes
3041 + u16 output_offset_x[PISP_BACK_END_NUM_OUTPUTS];
3042 + u16 output_offset_y[PISP_BACK_END_NUM_OUTPUTS];
3043 + u16 output_width[PISP_BACK_END_NUM_OUTPUTS];
3044 + u16 output_height[PISP_BACK_END_NUM_OUTPUTS];
3045 + // 140 bytes
3046 + u32 output_addr_offset[PISP_BACK_END_NUM_OUTPUTS];
3047 + u32 output_addr_offset2[PISP_BACK_END_NUM_OUTPUTS];
3048 + // 156 bytes
3049 + u32 output_hog_addr_offset;
3050 + // 160 bytes
3051 +};
3052 +
3053 +static_assert(sizeof(struct pisp_tile) == 160);
3054 +
3055 +struct pisp_be_tiles_config {
3056 + struct pisp_be_config config;
3057 + struct pisp_tile tiles[PISP_BACK_END_NUM_TILES];
3058 + int num_tiles;
3059 +};
3060 +
3061 +#endif /* _PISP_BE_CONFIG_H_ */
3062 --- /dev/null
3063 +++ b/drivers/media/platform/raspberrypi/pisp_be/pisp_be_formats.h
3064 @@ -0,0 +1,469 @@
3065 +/* SPDX-License-Identifier: GPL-2.0 */
3066 +/*
3067 + * PiSP Back End driver image format definitions.
3068 + *
3069 + * Copyright (c) 2021 Raspberry Pi Ltd
3070 + */
3071 +
3072 +#ifndef _PISP_BE_FORMATS_
3073 +#define _PISP_BE_FORMATS_
3074 +
3075 +#include <linux/bits.h>
3076 +#include <linux/videodev2.h>
3077 +
3078 +#define MAX_PLANES 3
3079 +#define P3(x) ((x) * 8)
3080 +
3081 +struct pisp_be_format {
3082 + unsigned int fourcc;
3083 + unsigned int align;
3084 + unsigned int bit_depth;
3085 + /* 0P3 factor for plane sizing */
3086 + unsigned int plane_factor[MAX_PLANES];
3087 + unsigned int num_planes;
3088 + unsigned int colorspace_mask;
3089 + enum v4l2_colorspace colorspace_default;
3090 +};
3091 +
3092 +#define V4L2_COLORSPACE_MASK(colorspace) BIT(colorspace)
3093 +
3094 +#define V4L2_COLORSPACE_MASK_JPEG V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_JPEG)
3095 +#define V4L2_COLORSPACE_MASK_SMPTE170M V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_SMPTE170M)
3096 +#define V4L2_COLORSPACE_MASK_REC709 V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_REC709)
3097 +#define V4L2_COLORSPACE_MASK_SRGB V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_SRGB)
3098 +#define V4L2_COLORSPACE_MASK_RAW V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_RAW)
3099 +
3100 +/*
3101 + * All three colour spaces JPEG, SMPTE170M and REC709 are fundamentally sRGB
3102 + * underneath (as near as makes no difference to us), just with different YCbCr
3103 + * encodings. Therefore the ISP can generate sRGB on its main output and any of
3104 + * the others on its low resolution output. Applications should, when using both
3105 + * outputs, program the colour spaces on them to be the same, matching whatever
3106 + * is requested for the low resolution output, even if the main output is
3107 + * producing an RGB format. In turn this requires us to allow all these colour
3108 + * spaces for every YUV/RGB output format.
3109 + */
3110 +#define V4L2_COLORSPACE_MASK_ALL_SRGB (V4L2_COLORSPACE_MASK_JPEG | \
3111 + V4L2_COLORSPACE_MASK_SRGB | \
3112 + V4L2_COLORSPACE_MASK_SMPTE170M | \
3113 + V4L2_COLORSPACE_MASK_REC709)
3114 +
3115 +static const struct pisp_be_format supported_formats[] = {
3116 + /* Single plane YUV formats */
3117 + {
3118 + .fourcc = V4L2_PIX_FMT_YUV420,
3119 + /* 128 alignment to ensure U/V planes are 64 byte aligned. */
3120 + .align = 128,
3121 + .bit_depth = 8,
3122 + .plane_factor = { P3(1), P3(0.25), P3(0.25) },
3123 + .num_planes = 1,
3124 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3125 + .colorspace_default = V4L2_COLORSPACE_JPEG,
3126 + },
3127 + {
3128 + .fourcc = V4L2_PIX_FMT_YVU420,
3129 + /* 128 alignment to ensure U/V planes are 64 byte aligned. */
3130 + .align = 128,
3131 + .bit_depth = 8,
3132 + .plane_factor = { P3(1), P3(0.25), P3(0.25) },
3133 + .num_planes = 1,
3134 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3135 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3136 + },
3137 + {
3138 + .fourcc = V4L2_PIX_FMT_NV12,
3139 + .align = 32,
3140 + .bit_depth = 8,
3141 + .plane_factor = { P3(1), P3(0.5) },
3142 + .num_planes = 1,
3143 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3144 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3145 + },
3146 + {
3147 + .fourcc = V4L2_PIX_FMT_NV21,
3148 + .align = 32,
3149 + .bit_depth = 8,
3150 + .plane_factor = { P3(1), P3(0.5) },
3151 + .num_planes = 1,
3152 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3153 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3154 + },
3155 + {
3156 + .fourcc = V4L2_PIX_FMT_YUYV,
3157 + .align = 64,
3158 + .bit_depth = 16,
3159 + .plane_factor = { P3(1) },
3160 + .num_planes = 1,
3161 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3162 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3163 + },
3164 + {
3165 + .fourcc = V4L2_PIX_FMT_UYVY,
3166 + .align = 64,
3167 + .bit_depth = 16,
3168 + .plane_factor = { P3(1) },
3169 + .num_planes = 1,
3170 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3171 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3172 + },
3173 + {
3174 + .fourcc = V4L2_PIX_FMT_YVYU,
3175 + .align = 64,
3176 + .bit_depth = 16,
3177 + .plane_factor = { P3(1) },
3178 + .num_planes = 1,
3179 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3180 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3181 + },
3182 + {
3183 + .fourcc = V4L2_PIX_FMT_VYUY,
3184 + .align = 64,
3185 + .bit_depth = 16,
3186 + .plane_factor = { P3(1) },
3187 + .num_planes = 1,
3188 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3189 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3190 + },
3191 + /* Multiplane YUV formats */
3192 + {
3193 + .fourcc = V4L2_PIX_FMT_YUV420M,
3194 + .align = 64,
3195 + .bit_depth = 8,
3196 + .plane_factor = { P3(1), P3(0.25), P3(0.25) },
3197 + .num_planes = 3,
3198 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3199 + .colorspace_default = V4L2_COLORSPACE_JPEG,
3200 + },
3201 + {
3202 + .fourcc = V4L2_PIX_FMT_NV12M,
3203 + .align = 32,
3204 + .bit_depth = 8,
3205 + .plane_factor = { P3(1), P3(0.5) },
3206 + .num_planes = 2,
3207 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3208 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3209 + },
3210 + {
3211 + .fourcc = V4L2_PIX_FMT_NV21M,
3212 + .align = 32,
3213 + .bit_depth = 8,
3214 + .plane_factor = { P3(1), P3(0.5) },
3215 + .num_planes = 2,
3216 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3217 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3218 + },
3219 + {
3220 + .fourcc = V4L2_PIX_FMT_YVU420M,
3221 + .align = 64,
3222 + .bit_depth = 8,
3223 + .plane_factor = { P3(1), P3(0.25), P3(0.25) },
3224 + .num_planes = 3,
3225 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3226 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3227 + },
3228 + {
3229 + .fourcc = V4L2_PIX_FMT_YUV422M,
3230 + .align = 64,
3231 + .bit_depth = 8,
3232 + .plane_factor = { P3(1), P3(0.5), P3(0.5) },
3233 + .num_planes = 3,
3234 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3235 + .colorspace_default = V4L2_COLORSPACE_JPEG,
3236 + },
3237 + {
3238 + .fourcc = V4L2_PIX_FMT_YVU422M,
3239 + .align = 64,
3240 + .bit_depth = 8,
3241 + .plane_factor = { P3(1), P3(0.5), P3(0.5) },
3242 + .num_planes = 3,
3243 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3244 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3245 + },
3246 + {
3247 + .fourcc = V4L2_PIX_FMT_YUV444M,
3248 + .align = 64,
3249 + .bit_depth = 8,
3250 + .plane_factor = { P3(1), P3(1), P3(1) },
3251 + .num_planes = 3,
3252 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3253 + .colorspace_default = V4L2_COLORSPACE_JPEG,
3254 + },
3255 + {
3256 + .fourcc = V4L2_PIX_FMT_YVU444M,
3257 + .align = 64,
3258 + .bit_depth = 8,
3259 + .plane_factor = { P3(1), P3(1), P3(1) },
3260 + .num_planes = 3,
3261 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3262 + .colorspace_default = V4L2_COLORSPACE_SMPTE170M,
3263 + },
3264 + /* RGB formats */
3265 + {
3266 + .fourcc = V4L2_PIX_FMT_RGB24,
3267 + .align = 32,
3268 + .bit_depth = 24,
3269 + .plane_factor = { P3(1.0) },
3270 + .num_planes = 1,
3271 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3272 + .colorspace_default = V4L2_COLORSPACE_SRGB,
3273 + },
3274 + {
3275 + .fourcc = V4L2_PIX_FMT_BGR24,
3276 + .align = 32,
3277 + .bit_depth = 24,
3278 + .plane_factor = { P3(1.0) },
3279 + .num_planes = 1,
3280 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3281 + .colorspace_default = V4L2_COLORSPACE_SRGB,
3282 + },
3283 + {
3284 + .fourcc = V4L2_PIX_FMT_XBGR32,
3285 + .align = 64,
3286 + .bit_depth = 32,
3287 + .plane_factor = { P3(1.0) },
3288 + .num_planes = 1,
3289 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3290 + .colorspace_default = V4L2_COLORSPACE_SRGB,
3291 + },
3292 + {
3293 + .fourcc = V4L2_PIX_FMT_RGBX32,
3294 + .align = 64,
3295 + .bit_depth = 32,
3296 + .plane_factor = { P3(1.0) },
3297 + .num_planes = 1,
3298 + .colorspace_mask = V4L2_COLORSPACE_MASK_ALL_SRGB,
3299 + .colorspace_default = V4L2_COLORSPACE_SRGB,
3300 + },
3301 + /* Bayer formats - 8-bit */
3302 + {
3303 + .fourcc = V4L2_PIX_FMT_SRGGB8,
3304 + .bit_depth = 8,
3305 + .align = 32,
3306 + .plane_factor = { P3(1.0) },
3307 + .num_planes = 1,
3308 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3309 + .colorspace_default = V4L2_COLORSPACE_RAW,
3310 + },
3311 + {
3312 + .fourcc = V4L2_PIX_FMT_SBGGR8,
3313 + .bit_depth = 8,
3314 + .align = 32,
3315 + .plane_factor = { P3(1.0) },
3316 + .num_planes = 1,
3317 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3318 + .colorspace_default = V4L2_COLORSPACE_RAW,
3319 + },
3320 + {
3321 + .fourcc = V4L2_PIX_FMT_SGRBG8,
3322 + .bit_depth = 8,
3323 + .align = 32,
3324 + .plane_factor = { P3(1.0) },
3325 + .num_planes = 1,
3326 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3327 + .colorspace_default = V4L2_COLORSPACE_RAW,
3328 + },
3329 + {
3330 + .fourcc = V4L2_PIX_FMT_SGBRG8,
3331 + .bit_depth = 8,
3332 + .align = 32,
3333 + .plane_factor = { P3(1.0) },
3334 + .num_planes = 1,
3335 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3336 + .colorspace_default = V4L2_COLORSPACE_RAW,
3337 + },
3338 + /* Bayer formats - 16-bit */
3339 + {
3340 + .fourcc = V4L2_PIX_FMT_SRGGB16,
3341 + .bit_depth = 16,
3342 + .align = 32,
3343 + .plane_factor = { P3(1.0) },
3344 + .num_planes = 1,
3345 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3346 + .colorspace_default = V4L2_COLORSPACE_RAW,
3347 + },
3348 + {
3349 + .fourcc = V4L2_PIX_FMT_SBGGR16,
3350 + .bit_depth = 16,
3351 + .align = 32,
3352 + .plane_factor = { P3(1.0) },
3353 + .num_planes = 1,
3354 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3355 + .colorspace_default = V4L2_COLORSPACE_RAW,
3356 + },
3357 + {
3358 + .fourcc = V4L2_PIX_FMT_SGRBG16,
3359 + .bit_depth = 16,
3360 + .align = 32,
3361 + .plane_factor = { P3(1.0) },
3362 + .num_planes = 1,
3363 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3364 + .colorspace_default = V4L2_COLORSPACE_RAW,
3365 + },
3366 + {
3367 + .fourcc = V4L2_PIX_FMT_SGBRG16,
3368 + .bit_depth = 16,
3369 + .align = 32,
3370 + .plane_factor = { P3(1.0) },
3371 + .num_planes = 1,
3372 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3373 + .colorspace_default = V4L2_COLORSPACE_RAW,
3374 + },
3375 + {
3376 + /* Bayer formats unpacked to 16bpp */
3377 + /* 10 bit */
3378 + .fourcc = V4L2_PIX_FMT_SRGGB10,
3379 + .bit_depth = 16,
3380 + .align = 32,
3381 + .plane_factor = { P3(1.0) },
3382 + .num_planes = 1,
3383 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3384 + .colorspace_default = V4L2_COLORSPACE_RAW,
3385 + },
3386 + {
3387 + .fourcc = V4L2_PIX_FMT_SBGGR10,
3388 + .bit_depth = 16,
3389 + .align = 32,
3390 + .plane_factor = { P3(1.0) },
3391 + .num_planes = 1,
3392 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3393 + .colorspace_default = V4L2_COLORSPACE_RAW,
3394 + },
3395 + {
3396 + .fourcc = V4L2_PIX_FMT_SGRBG10,
3397 + .bit_depth = 16,
3398 + .align = 32,
3399 + .plane_factor = { P3(1.0) },
3400 + .num_planes = 1,
3401 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3402 + .colorspace_default = V4L2_COLORSPACE_RAW,
3403 + },
3404 + {
3405 + .fourcc = V4L2_PIX_FMT_SGBRG10,
3406 + .bit_depth = 16,
3407 + .align = 32,
3408 + .plane_factor = { P3(1.0) },
3409 + .num_planes = 1,
3410 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3411 + .colorspace_default = V4L2_COLORSPACE_RAW,
3412 + },
3413 + {
3414 + /* 12 bit */
3415 + .fourcc = V4L2_PIX_FMT_SRGGB12,
3416 + .bit_depth = 16,
3417 + .align = 32,
3418 + .plane_factor = { P3(1.0) },
3419 + .num_planes = 1,
3420 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3421 + .colorspace_default = V4L2_COLORSPACE_RAW,
3422 + },
3423 + {
3424 + .fourcc = V4L2_PIX_FMT_SBGGR12,
3425 + .bit_depth = 16,
3426 + .align = 32,
3427 + .plane_factor = { P3(1.0) },
3428 + .num_planes = 1,
3429 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3430 + .colorspace_default = V4L2_COLORSPACE_RAW,
3431 + },
3432 + {
3433 + .fourcc = V4L2_PIX_FMT_SGRBG12,
3434 + .bit_depth = 16,
3435 + .align = 32,
3436 + .plane_factor = { P3(1.0) },
3437 + .num_planes = 1,
3438 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3439 + .colorspace_default = V4L2_COLORSPACE_RAW,
3440 + },
3441 + {
3442 + .fourcc = V4L2_PIX_FMT_SGBRG12,
3443 + .bit_depth = 16,
3444 + .align = 32,
3445 + .plane_factor = { P3(1.0) },
3446 + .num_planes = 1,
3447 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3448 + .colorspace_default = V4L2_COLORSPACE_RAW,
3449 + },
3450 + {
3451 + /* 14 bit */
3452 + .fourcc = V4L2_PIX_FMT_SRGGB14,
3453 + .bit_depth = 16,
3454 + .align = 32,
3455 + .plane_factor = { P3(1.0) },
3456 + .num_planes = 1,
3457 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3458 + .colorspace_default = V4L2_COLORSPACE_RAW,
3459 + },
3460 + {
3461 + .fourcc = V4L2_PIX_FMT_SBGGR14,
3462 + .bit_depth = 16,
3463 + .align = 32,
3464 + .plane_factor = { P3(1.0) },
3465 + .num_planes = 1,
3466 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3467 + .colorspace_default = V4L2_COLORSPACE_RAW,
3468 + },
3469 + {
3470 + .fourcc = V4L2_PIX_FMT_SGRBG14,
3471 + .bit_depth = 16,
3472 + .align = 32,
3473 + .plane_factor = { P3(1.0) },
3474 + .num_planes = 1,
3475 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3476 + .colorspace_default = V4L2_COLORSPACE_RAW,
3477 + },
3478 + {
3479 + .fourcc = V4L2_PIX_FMT_SGBRG14,
3480 + .bit_depth = 16,
3481 + .align = 32,
3482 + .plane_factor = { P3(1.0) },
3483 + .num_planes = 1,
3484 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3485 + .colorspace_default = V4L2_COLORSPACE_RAW,
3486 + },
3487 + /* Bayer formats - 16-bit PiSP Compressed */
3488 + {
3489 + .fourcc = V4L2_PIX_FMT_PISP_COMP1_BGGR,
3490 + .bit_depth = 8,
3491 + .align = 32,
3492 + .plane_factor = { P3(1.0) },
3493 + .num_planes = 1,
3494 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3495 + .colorspace_default = V4L2_COLORSPACE_RAW,
3496 + },
3497 + {
3498 + .fourcc = V4L2_PIX_FMT_PISP_COMP1_RGGB,
3499 + .bit_depth = 8,
3500 + .align = 32,
3501 + .plane_factor = { P3(1.0) },
3502 + .num_planes = 1,
3503 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3504 + .colorspace_default = V4L2_COLORSPACE_RAW,
3505 + },
3506 + {
3507 + .fourcc = V4L2_PIX_FMT_PISP_COMP1_GRBG,
3508 + .bit_depth = 8,
3509 + .align = 32,
3510 + .plane_factor = { P3(1.0) },
3511 + .num_planes = 1,
3512 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3513 + .colorspace_default = V4L2_COLORSPACE_RAW,
3514 + },
3515 + {
3516 + .fourcc = V4L2_PIX_FMT_PISP_COMP1_GBRG,
3517 + .bit_depth = 8,
3518 + .align = 32,
3519 + .plane_factor = { P3(1.0) },
3520 + .num_planes = 1,
3521 + .colorspace_mask = V4L2_COLORSPACE_MASK_RAW,
3522 + .colorspace_default = V4L2_COLORSPACE_RAW,
3523 + },
3524 +};
3525 +
3526 +static const struct pisp_be_format meta_out_supported_formats[] = {
3527 + /* Configuration buffer format. */
3528 + {
3529 + .fourcc = V4L2_META_FMT_RPI_BE_CFG,
3530 + },
3531 +};
3532 +
3533 +#endif /* _PISP_BE_FORMATS_ */
3534 --- a/drivers/media/v4l2-core/v4l2-ioctl.c
3535 +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
3536 @@ -1452,6 +1452,7 @@ static void v4l_fill_fmtdesc(struct v4l2
3537 case V4L2_PIX_FMT_NV12M_10BE_8L128: descr = "10-bit NV12M (8x128 Linear, BE)"; break;
3538 case V4L2_META_FMT_SENSOR_DATA: descr = "Sensor Ancillary Metadata"; break;
3539 case V4L2_META_FMT_BCM2835_ISP_STATS: descr = "BCM2835 ISP Image Statistics"; break;
3540 + case V4L2_META_FMT_RPI_BE_CFG: descr = "PiSP Config format"; break;
3541
3542 default:
3543 /* Compressed formats */
3544 @@ -1503,6 +1504,7 @@ static void v4l_fill_fmtdesc(struct v4l2
3545 case V4L2_PIX_FMT_MT21C: descr = "Mediatek Compressed Format"; break;
3546 case V4L2_PIX_FMT_QC08C: descr = "QCOM Compressed 8-bit Format"; break;
3547 case V4L2_PIX_FMT_QC10C: descr = "QCOM Compressed 10-bit Format"; break;
3548 + case V4L2_PIX_FMT_RPI_BE: descr = "PiSP Opaque Format"; break;
3549 default:
3550 if (fmt->description[0])
3551 return;
3552 --- /dev/null
3553 +++ b/include/media/raspberrypi/pisp_common.h
3554 @@ -0,0 +1,65 @@
3555 +/* SPDX-License-Identifier: GPL-2.0-only */
3556 +/*
3557 + * Raspberry Pi PiSP common configuration definitions.
3558 + *
3559 + * Copyright (C) 2021 - Raspberry Pi (Trading) Ltd.
3560 + *
3561 + */
3562 +#ifndef _PISP_COMMON_H_
3563 +#define _PISP_COMMON_H_
3564 +
3565 +#include <linux/types.h>
3566 +
3567 +#include "pisp_types.h"
3568 +
3569 +struct pisp_bla_config {
3570 + uint16_t black_level_r;
3571 + uint16_t black_level_gr;
3572 + uint16_t black_level_gb;
3573 + uint16_t black_level_b;
3574 + uint16_t output_black_level;
3575 + uint8_t pad[2];
3576 +};
3577 +
3578 +struct pisp_wbg_config {
3579 + uint16_t gain_r;
3580 + uint16_t gain_g;
3581 + uint16_t gain_b;
3582 + uint8_t pad[2];
3583 +};
3584 +
3585 +struct pisp_compress_config {
3586 + /* value subtracted from incoming data */
3587 + uint16_t offset;
3588 + uint8_t pad;
3589 + /* 1 => Companding; 2 => Delta (recommended); 3 => Combined (for HDR) */
3590 + uint8_t mode;
3591 +};
3592 +
3593 +struct pisp_decompress_config {
3594 + /* value added to reconstructed data */
3595 + uint16_t offset;
3596 + uint8_t pad;
3597 + /* 1 => Companding; 2 => Delta (recommended); 3 => Combined (for HDR) */
3598 + uint8_t mode;
3599 +};
3600 +
3601 +enum pisp_axi_flags {
3602 + /* round down bursts to end at a 32-byte boundary, to align following bursts */
3603 + PISP_AXI_FLAG_ALIGN = 128,
3604 + /* for FE writer: force WSTRB high, to pad output to 16-byte boundary */
3605 + PISP_AXI_FLAG_PAD = 64,
3606 + /* for FE writer: Use Output FIFO level to trigger "panic" */
3607 + PISP_AXI_FLAG_PANIC = 32
3608 +};
3609 +
3610 +struct pisp_axi_config {
3611 + /* burst length minus one, which must be in the range 0:15; OR'd with flags */
3612 + uint8_t maxlen_flags;
3613 + /* { prot[2:0], cache[3:0] } fields, echoed on AXI bus */
3614 + uint8_t cache_prot;
3615 + /* QoS field(s) (4x4 bits for FE writer; 4 bits for other masters) */
3616 + uint16_t qos;
3617 +};
3618 +
3619 +#endif /* _PISP_COMMON_H_ */
3620 --- /dev/null
3621 +++ b/include/media/raspberrypi/pisp_types.h
3622 @@ -0,0 +1,144 @@
3623 +/* SPDX-License-Identifier: GPL-2.0-only */
3624 +/*
3625 + * Raspberry Pi PiSP common types.
3626 + *
3627 + * Copyright (C) 2021 - Raspberry Pi (Trading) Ltd.
3628 + *
3629 + */
3630 +#ifndef _PISP_TYPES_H_
3631 +#define _PISP_TYPES_H_
3632 +
3633 +/* This definition must match the format description in the hardware exactly! */
3634 +struct pisp_image_format_config {
3635 + /* size in pixels */
3636 + uint16_t width, height;
3637 + /* must match struct pisp_image_format below */
3638 + uint32_t format;
3639 + int32_t stride;
3640 + /* some planar image formats will need a second stride */
3641 + int32_t stride2;
3642 +};
3643 +
3644 +static_assert(sizeof(struct pisp_image_format_config) == 16);
3645 +
3646 +enum pisp_bayer_order {
3647 + /*
3648 + * Note how bayer_order&1 tells you if G is on the even pixels of the
3649 + * checkerboard or not, and bayer_order&2 tells you if R is on the even
3650 + * rows or is swapped with B. Note that if the top (of the 8) bits is
3651 + * set, this denotes a monochrome or greyscale image, and the lower bits
3652 + * should all be ignored.
3653 + */
3654 + PISP_BAYER_ORDER_RGGB = 0,
3655 + PISP_BAYER_ORDER_GBRG = 1,
3656 + PISP_BAYER_ORDER_BGGR = 2,
3657 + PISP_BAYER_ORDER_GRBG = 3,
3658 + PISP_BAYER_ORDER_GREYSCALE = 128
3659 +};
3660 +
3661 +enum pisp_image_format {
3662 + /*
3663 + * Precise values are mostly tbd. Generally these will be portmanteau
3664 + * values comprising bit fields and flags. This format must be shared
3665 + * throughout the PiSP.
3666 + */
3667 + PISP_IMAGE_FORMAT_BPS_8 = 0x00000000,
3668 + PISP_IMAGE_FORMAT_BPS_10 = 0x00000001,
3669 + PISP_IMAGE_FORMAT_BPS_12 = 0x00000002,
3670 + PISP_IMAGE_FORMAT_BPS_16 = 0x00000003,
3671 + PISP_IMAGE_FORMAT_BPS_MASK = 0x00000003,
3672 +
3673 + PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED = 0x00000000,
3674 + PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR = 0x00000010,
3675 + PISP_IMAGE_FORMAT_PLANARITY_PLANAR = 0x00000020,
3676 + PISP_IMAGE_FORMAT_PLANARITY_MASK = 0x00000030,
3677 +
3678 + PISP_IMAGE_FORMAT_SAMPLING_444 = 0x00000000,
3679 + PISP_IMAGE_FORMAT_SAMPLING_422 = 0x00000100,
3680 + PISP_IMAGE_FORMAT_SAMPLING_420 = 0x00000200,
3681 + PISP_IMAGE_FORMAT_SAMPLING_MASK = 0x00000300,
3682 +
3683 + PISP_IMAGE_FORMAT_ORDER_NORMAL = 0x00000000,
3684 + PISP_IMAGE_FORMAT_ORDER_SWAPPED = 0x00001000,
3685 +
3686 + PISP_IMAGE_FORMAT_SHIFT_0 = 0x00000000,
3687 + PISP_IMAGE_FORMAT_SHIFT_1 = 0x00010000,
3688 + PISP_IMAGE_FORMAT_SHIFT_2 = 0x00020000,
3689 + PISP_IMAGE_FORMAT_SHIFT_3 = 0x00030000,
3690 + PISP_IMAGE_FORMAT_SHIFT_4 = 0x00040000,
3691 + PISP_IMAGE_FORMAT_SHIFT_5 = 0x00050000,
3692 + PISP_IMAGE_FORMAT_SHIFT_6 = 0x00060000,
3693 + PISP_IMAGE_FORMAT_SHIFT_7 = 0x00070000,
3694 + PISP_IMAGE_FORMAT_SHIFT_8 = 0x00080000,
3695 + PISP_IMAGE_FORMAT_SHIFT_MASK = 0x000f0000,
3696 +
3697 + PISP_IMAGE_FORMAT_UNCOMPRESSED = 0x00000000,
3698 + PISP_IMAGE_FORMAT_COMPRESSION_MODE_1 = 0x01000000,
3699 + PISP_IMAGE_FORMAT_COMPRESSION_MODE_2 = 0x02000000,
3700 + PISP_IMAGE_FORMAT_COMPRESSION_MODE_3 = 0x03000000,
3701 + PISP_IMAGE_FORMAT_COMPRESSION_MASK = 0x03000000,
3702 +
3703 + PISP_IMAGE_FORMAT_HOG_SIGNED = 0x04000000,
3704 + PISP_IMAGE_FORMAT_HOG_UNSIGNED = 0x08000000,
3705 + PISP_IMAGE_FORMAT_INTEGRAL_IMAGE = 0x10000000,
3706 + PISP_IMAGE_FORMAT_WALLPAPER_ROLL = 0x20000000,
3707 + PISP_IMAGE_FORMAT_THREE_CHANNEL = 0x40000000,
3708 +
3709 + /* Lastly a few specific instantiations of the above. */
3710 + PISP_IMAGE_FORMAT_SINGLE_16 = PISP_IMAGE_FORMAT_BPS_16,
3711 + PISP_IMAGE_FORMAT_THREE_16 =
3712 + PISP_IMAGE_FORMAT_BPS_16 | PISP_IMAGE_FORMAT_THREE_CHANNEL
3713 +};
3714 +
3715 +#define PISP_IMAGE_FORMAT_bps_8(fmt) \
3716 + (((fmt)&PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_8)
3717 +#define PISP_IMAGE_FORMAT_bps_10(fmt) \
3718 + (((fmt)&PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_10)
3719 +#define PISP_IMAGE_FORMAT_bps_12(fmt) \
3720 + (((fmt)&PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_12)
3721 +#define PISP_IMAGE_FORMAT_bps_16(fmt) \
3722 + (((fmt)&PISP_IMAGE_FORMAT_BPS_MASK) == PISP_IMAGE_FORMAT_BPS_16)
3723 +#define PISP_IMAGE_FORMAT_bps(fmt) \
3724 + (((fmt)&PISP_IMAGE_FORMAT_BPS_MASK) ? \
3725 + 8 + (2 << (((fmt)&PISP_IMAGE_FORMAT_BPS_MASK) - 1)) : \
3726 + 8)
3727 +#define PISP_IMAGE_FORMAT_shift(fmt) \
3728 + (((fmt)&PISP_IMAGE_FORMAT_SHIFT_MASK) / PISP_IMAGE_FORMAT_SHIFT_1)
3729 +#define PISP_IMAGE_FORMAT_three_channel(fmt) \
3730 + ((fmt)&PISP_IMAGE_FORMAT_THREE_CHANNEL)
3731 +#define PISP_IMAGE_FORMAT_single_channel(fmt) \
3732 + (!((fmt)&PISP_IMAGE_FORMAT_THREE_CHANNEL))
3733 +#define PISP_IMAGE_FORMAT_compressed(fmt) \
3734 + (((fmt)&PISP_IMAGE_FORMAT_COMPRESSION_MASK) != \
3735 + PISP_IMAGE_FORMAT_UNCOMPRESSED)
3736 +#define PISP_IMAGE_FORMAT_sampling_444(fmt) \
3737 + (((fmt)&PISP_IMAGE_FORMAT_SAMPLING_MASK) == \
3738 + PISP_IMAGE_FORMAT_SAMPLING_444)
3739 +#define PISP_IMAGE_FORMAT_sampling_422(fmt) \
3740 + (((fmt)&PISP_IMAGE_FORMAT_SAMPLING_MASK) == \
3741 + PISP_IMAGE_FORMAT_SAMPLING_422)
3742 +#define PISP_IMAGE_FORMAT_sampling_420(fmt) \
3743 + (((fmt)&PISP_IMAGE_FORMAT_SAMPLING_MASK) == \
3744 + PISP_IMAGE_FORMAT_SAMPLING_420)
3745 +#define PISP_IMAGE_FORMAT_order_normal(fmt) \
3746 + (!((fmt)&PISP_IMAGE_FORMAT_ORDER_SWAPPED))
3747 +#define PISP_IMAGE_FORMAT_order_swapped(fmt) \
3748 + ((fmt)&PISP_IMAGE_FORMAT_ORDER_SWAPPED)
3749 +#define PISP_IMAGE_FORMAT_interleaved(fmt) \
3750 + (((fmt)&PISP_IMAGE_FORMAT_PLANARITY_MASK) == \
3751 + PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED)
3752 +#define PISP_IMAGE_FORMAT_semiplanar(fmt) \
3753 + (((fmt)&PISP_IMAGE_FORMAT_PLANARITY_MASK) == \
3754 + PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR)
3755 +#define PISP_IMAGE_FORMAT_planar(fmt) \
3756 + (((fmt)&PISP_IMAGE_FORMAT_PLANARITY_MASK) == \
3757 + PISP_IMAGE_FORMAT_PLANARITY_PLANAR)
3758 +#define PISP_IMAGE_FORMAT_wallpaper(fmt) \
3759 + ((fmt)&PISP_IMAGE_FORMAT_WALLPAPER_ROLL)
3760 +#define PISP_IMAGE_FORMAT_HOG(fmt) \
3761 + ((fmt) & \
3762 + (PISP_IMAGE_FORMAT_HOG_SIGNED | PISP_IMAGE_FORMAT_HOG_UNSIGNED))
3763 +
3764 +#define PISP_WALLPAPER_WIDTH 128 // in bytes
3765 +
3766 +#endif /* _PISP_TYPES_H_ */
3767 --- a/include/uapi/linux/videodev2.h
3768 +++ b/include/uapi/linux/videodev2.h
3769 @@ -793,6 +793,9 @@ struct v4l2_pix_format {
3770 #define V4L2_PIX_FMT_IPU3_SGRBG10 v4l2_fourcc('i', 'p', '3', 'G') /* IPU3 packed 10-bit GRBG bayer */
3771 #define V4L2_PIX_FMT_IPU3_SRGGB10 v4l2_fourcc('i', 'p', '3', 'r') /* IPU3 packed 10-bit RGGB bayer */
3772
3773 +/* The pixel format for all our buffers (the precise format is found in the config buffer). */
3774 +#define V4L2_PIX_FMT_RPI_BE v4l2_fourcc('R', 'P', 'B', 'P')
3775 +
3776 /* SDR formats - used only for Software Defined Radio devices */
3777 #define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */
3778 #define V4L2_SDR_FMT_CU16LE v4l2_fourcc('C', 'U', '1', '6') /* IQ u16le */
3779 @@ -822,6 +825,9 @@ struct v4l2_pix_format {
3780 #define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 3A Parameters */
3781 #define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A Statistics */
3782
3783 +/* The metadata format identifier for our configuration buffers. */
3784 +#define V4L2_META_FMT_RPI_BE_CFG v4l2_fourcc('R', 'P', 'B', 'C')
3785 +
3786 /* priv field value to indicates that subsequent fields are valid. */
3787 #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe
3788
Staging tree of Piotr Dymacz