git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From aa8b6bd2b1f235b262bd27f317a0516f196c2c6a Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Tue, 23 May 2023 11:15:58 +0100
   4 Subject: [PATCH 18/21] net: phylink: add function to resolve clause 73
   5  negotiation
   6
   7 Add a function to resolve clause 73 negotiation according to the
   8 priority resolution function described in clause 73.3.6.
   9
  10 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  13 ---
  14  drivers/net/phy/phylink.c | 39 +++++++++++++++++++++++++++++++++++++++
  15  include/linux/phylink.h   |  2 ++
  16  2 files changed, 41 insertions(+)
  17
  18 --- a/drivers/net/phy/phylink.c
  19 +++ b/drivers/net/phy/phylink.c
  20 @@ -3212,6 +3212,45 @@ static const struct sfp_upstream_ops sfp
  21
  22  /* Helpers for MAC drivers */
  23
  24 +static struct {
  25 +       int bit;
  26 +       int speed;
  27 +} phylink_c73_priority_resolution[] = {
  28 +       { ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, SPEED_100000 },
  29 +       { ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, SPEED_100000 },
  30 +       /* 100GBASE-KP4 and 100GBASE-CR10 not supported */
  31 +       { ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, SPEED_40000 },
  32 +       { ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, SPEED_40000 },
  33 +       { ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, SPEED_10000 },
  34 +       { ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, SPEED_10000 },
  35 +       /* 5GBASE-KR not supported */
  36 +       { ETHTOOL_LINK_MODE_2500baseX_Full_BIT, SPEED_2500 },
  37 +       { ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, SPEED_1000 },
  38 +};
  39 +
  40 +void phylink_resolve_c73(struct phylink_link_state *state)
  41 +{
  42 +       int i;
  43 +
  44 +       for (i = 0; i < ARRAY_SIZE(phylink_c73_priority_resolution); i++) {
  45 +               int bit = phylink_c73_priority_resolution[i].bit;
  46 +               if (linkmode_test_bit(bit, state->advertising) &&
  47 +                   linkmode_test_bit(bit, state->lp_advertising))
  48 +                       break;
  49 +       }
  50 +
  51 +       if (i < ARRAY_SIZE(phylink_c73_priority_resolution)) {
  52 +               state->speed = phylink_c73_priority_resolution[i].speed;
  53 +               state->duplex = DUPLEX_FULL;
  54 +       } else {
  55 +               /* negotiation failure */
  56 +               state->link = false;
  57 +       }
  58 +
  59 +       phylink_resolve_an_pause(state);
  60 +}
  61 +EXPORT_SYMBOL_GPL(phylink_resolve_c73);
  62 +
  63  static void phylink_decode_c37_word(struct phylink_link_state *state,
  64                                     uint16_t config_reg, int speed)
  65  {
  66 --- a/include/linux/phylink.h
  67 +++ b/include/linux/phylink.h
  68 @@ -656,6 +656,8 @@ int phylink_mii_c22_pcs_config(struct md
  69                                const unsigned long *advertising);
  70  void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
  71
  72 +void phylink_resolve_c73(struct phylink_link_state *state);
  73 +
  74  void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
  75                                    struct phylink_link_state *state);
  76