git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From d5377dd13e91af81f8f31e93532c62216842038c Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Fri, 26 Apr 2024 19:20:41 +0100
   4 Subject: [PATCH 1070/1085] drm/panel-simple: Increase pixel clock on Pi 7inch
   5  panel
   6
   7 The Toshiba bridge is very fussy and doesn't like the CM3
   8 output when being told to produce a 27.777MHz pixel clock, which
   9 is an almost perfect match to the DSI link integer divider.
  10
  11 Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz
  12 and makes the bridge happy with the same video timing as works
  13 on Pi4.
  14 (Pi4 will be using a link frequency of 375MHz due to a 3GHz
  15 parent PLL).
  16
  17 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  18 ---
  19  drivers/gpu/drm/panel/panel-simple.c | 8 ++++----
  20  1 file changed, 4 insertions(+), 4 deletions(-)
  21
  22 --- a/drivers/gpu/drm/panel/panel-simple.c
  23 +++ b/drivers/gpu/drm/panel/panel-simple.c
  24 @@ -3416,11 +3416,11 @@ static const struct panel_desc rocktech_
  25  };
  26
  27  static const struct drm_display_mode raspberrypi_7inch_mode = {
  28 -       .clock = 27777,
  29 +       .clock = 30000,
  30         .hdisplay = 800,
  31 -       .hsync_start = 800 + 59,
  32 -       .hsync_end = 800 + 59 + 2,
  33 -       .htotal = 800 + 59 + 2 + 45,
  34 +       .hsync_start = 800 + 131,
  35 +       .hsync_end = 800 + 131 + 2,
  36 +       .htotal = 800 + 131 + 2 + 45,
  37         .vdisplay = 480,
  38         .vsync_start = 480 + 7,
  39         .vsync_end = 480 + 7 + 2,