git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 2e891d3d62f5fd51e33ae6e614198ce0b3b48e95 Mon Sep 17 00:00:00 2001
   2 From: Viorel Suman <viorel.suman@nxp.com>
   3 Date: Wed, 6 Jun 2018 13:36:20 +0300
   4 Subject: [PATCH] MLK-18534-1: ASoC: fsl: sai: introduce 1:1 bclk:mclk ratio
   5  support
   6
   7 Since IP version 3.01 (845s) SAI has support for 1:1
   8 bclk:mclk ratio.
   9
  10 Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
  11 ---
  12  sound/soc/fsl/fsl_sai.c | 69 +++++++++++++++++++++++++------------------------
  13  sound/soc/fsl/fsl_sai.h |  2 +-
  14  2 files changed, 36 insertions(+), 35 deletions(-)
  15
  16 --- a/sound/soc/fsl/fsl_sai.c
  17 +++ b/sound/soc/fsl/fsl_sai.c
  18 @@ -471,7 +471,8 @@ static int fsl_sai_set_bclk(struct snd_s
  19         struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
  20         unsigned char offset = sai->soc->reg_offset;
  21         unsigned long clk_rate;
  22 -       u32 savediv = 0, ratio, savesub = freq;
  23 +       unsigned int reg = 0;
  24 +       u32 ratio, savesub = freq, saveratio = 0, savediv = 0;
  25         u32 id;
  26         int ret = 0;
  27
  28 @@ -479,6 +480,8 @@ static int fsl_sai_set_bclk(struct snd_s
  29         if (sai->slave_mode[tx])
  30                 return 0;
  31
  32 +       fsl_sai_check_ver(dai);
  33 +
  34         for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
  35                 clk_rate = clk_get_rate(sai->mclk_clk[id]);
  36                 if (!clk_rate)
  37 @@ -499,22 +502,21 @@ static int fsl_sai_set_bclk(struct snd_s
  38                         "ratio %d for freq %dHz based on clock %ldHz\n",
  39                         ratio, freq, clk_rate);
  40
  41 -               if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
  42 -                       ratio /= 2;
  43 -               else
  44 -                       continue;
  45 +               if ((ratio % 2 == 0 && ratio >= 2 && ratio <= 512) ||
  46 +                   (ratio == 1 && sai->verid.id >= FSL_SAI_VERID_0301)) {
  47
  48 -               if (ret < savesub) {
  49 -                       savediv = ratio;
  50 -                       sai->mclk_id[tx] = id;
  51 -                       savesub = ret;
  52 -               }
  53 +                       if (ret < savesub) {
  54 +                               saveratio = ratio;
  55 +                               sai->mclk_id[tx] = id;
  56 +                               savesub = ret;
  57 +                       }
  58
  59 -               if (ret == 0)
  60 -                       break;
  61 +                       if (ret == 0)
  62 +                               break;
  63 +               }
  64         }
  65
  66 -       if (savediv == 0) {
  67 +       if (saveratio == 0) {
  68                 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
  69                                 tx ? 'T' : 'R', freq);
  70                 return -EINVAL;
  71 @@ -530,33 +532,32 @@ static int fsl_sai_set_bclk(struct snd_s
  72          * 4) For Tx and Rx are both Synchronous with another SAI, we just
  73          *    ignore it.
  74          */
  75 -       if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
  76 -           (!tx && !sai->synchronous[RX])) {
  77 -               regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset),
  78 -                                  FSL_SAI_CR2_MSEL_MASK,
  79 -                                  FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
  80 -               regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset),
  81 -                                  FSL_SAI_CR2_DIV_MASK, savediv - 1);
  82 -       } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
  83 -                  (tx && !sai->synchronous[TX])) {
  84 -               regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset),
  85 -                                  FSL_SAI_CR2_MSEL_MASK,
  86 -                                  FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
  87 -               regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset),
  88 -                                  FSL_SAI_CR2_DIV_MASK, savediv - 1);
  89 +       if ((!tx || sai->synchronous[TX]) && !sai->synchronous[RX])
  90 +               reg = FSL_SAI_RCR2(offset);
  91 +       else if ((tx || sai->synchronous[RX]) && !sai->synchronous[TX])
  92 +               reg = FSL_SAI_TCR2(offset);
  93 +
  94 +       if (reg) {
  95 +               regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
  96 +                          FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
  97 +
  98 +               savediv = (saveratio == 1 ? 0 : (saveratio >> 1) - 1);
  99 +               regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK, savediv);
 100 +
 101 +               if (sai->verid.id >= FSL_SAI_VERID_0301) {
 102 +                       regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_BYP,
 103 +                                  (saveratio == 1 ? FSL_SAI_CR2_BYP : 0));
 104 +               }
 105         }
 106
 107 -       fsl_sai_check_ver(dai);
 108 -       switch (sai->verid.id) {
 109 -       case FSL_SAI_VERID_0301:
 110 +       if (sai->verid.id >= FSL_SAI_VERID_0301) {
 111                 /* SAI is in master mode at this point, so enable MCLK */
 112                 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
 113 -                               FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
 114 -               break;
 115 +                       FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
 116         }
 117
 118 -       dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
 119 -                       sai->mclk_id[tx], savediv, savesub);
 120 +       dev_dbg(dai->dev, "best fit: clock id=%d, ratio=%d, deviation=%d\n",
 121 +                       sai->mclk_id[tx], saveratio, savesub);
 122
 123         return 0;
 124  }
 125 --- a/sound/soc/fsl/fsl_sai.h
 126 +++ b/sound/soc/fsl/fsl_sai.h
 127 @@ -122,7 +122,7 @@
 128  #define FSL_SAI_CR2_MSEL(ID)   ((ID) << 26)
 129  #define FSL_SAI_CR2_BCP                BIT(25)
 130  #define FSL_SAI_CR2_BCD_MSTR   BIT(24)
 131 -#define FSL_SAI_CR2_BCBP       BIT(23) /* BCLK bypass */
 132 +#define FSL_SAI_CR2_BYP                BIT(23) /* BCLK bypass */
 133  #define FSL_SAI_CR2_DIV_MASK   0xff
 134
 135  /* SAI Transmit and Receive Configuration 3 Register */