git.openwrt.org Git - openwrt/staging/neocturne.git/blob

   1 From fbfc4ca465a1f8d81bf2d67d95bf7fc67c3cf0c2 Mon Sep 17 00:00:00 2001
   2 From: Patrick Delaunay <patrick.delaunay@foss.st.com>
   3 Date: Fri, 18 Nov 2022 06:39:20 +0000
   4 Subject: [PATCH] nvmem: stm32: move STM32MP15_BSEC_NUM_LOWER in config
   5
   6 Support STM32MP15_BSEC_NUM_LOWER in stm32 romem config to prepare
   7 the next SoC in STM32MP family.
   8
   9 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
  10 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  11 Link: https://lore.kernel.org/r/20221118063932.6418-2-srinivas.kandagatla@linaro.org
  12 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  13 ---
  14  drivers/nvmem/stm32-romem.c | 21 ++++++++++++++++-----
  15  1 file changed, 16 insertions(+), 5 deletions(-)
  16
  17 --- a/drivers/nvmem/stm32-romem.c
  18 +++ b/drivers/nvmem/stm32-romem.c
  19 @@ -22,16 +22,15 @@
  20  /* shadow registers offest */
  21  #define STM32MP15_BSEC_DATA0           0x200
  22
  23 -/* 32 (x 32-bits) lower shadow registers */
  24 -#define STM32MP15_BSEC_NUM_LOWER       32
  25 -
  26  struct stm32_romem_cfg {
  27         int size;
  28 +       u8 lower;
  29  };
  30
  31  struct stm32_romem_priv {
  32         void __iomem *base;
  33         struct nvmem_config cfg;
  34 +       u8 lower;
  35  };
  36
  37  static int stm32_romem_read(void *context, unsigned int offset, void *buf,
  38 @@ -85,7 +84,7 @@ static int stm32_bsec_read(void *context
  39         for (i = roffset; (i < roffset + rbytes); i += 4) {
  40                 u32 otp = i >> 2;
  41
  42 -               if (otp < STM32MP15_BSEC_NUM_LOWER) {
  43 +               if (otp < priv->lower) {
  44                         /* read lower data from shadow registers */
  45                         val = readl_relaxed(
  46                                 priv->base + STM32MP15_BSEC_DATA0 + i);
  47 @@ -159,6 +158,8 @@ static int stm32_romem_probe(struct plat
  48         priv->cfg.priv = priv;
  49         priv->cfg.owner = THIS_MODULE;
  50
  51 +       priv->lower = 0;
  52 +
  53         cfg = (const struct stm32_romem_cfg *)
  54                 of_match_device(dev->driver->of_match_table, dev)->data;
  55         if (!cfg) {
  56 @@ -167,6 +168,7 @@ static int stm32_romem_probe(struct plat
  57                 priv->cfg.reg_read = stm32_romem_read;
  58         } else {
  59                 priv->cfg.size = cfg->size;
  60 +               priv->lower = cfg->lower;
  61                 priv->cfg.reg_read = stm32_bsec_read;
  62                 priv->cfg.reg_write = stm32_bsec_write;
  63         }
  64 @@ -174,8 +176,17 @@ static int stm32_romem_probe(struct plat
  65         return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
  66  }
  67
  68 +/*
  69 + * STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
  70 + * => 96 x 32-bits data words
  71 + * - Lower: 1K bits, 2:1 redundancy, incremental bit programming
  72 + *   => 32 (x 32-bits) lower shadow registers = words 0 to 31
  73 + * - Upper: 2K bits, ECC protection, word programming only
  74 + *   => 64 (x 32-bits) = words 32 to 95
  75 + */
  76  static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
  77 -       .size = 384, /* 96 x 32-bits data words */
  78 +       .size = 384,
  79 +       .lower = 32,
  80  };
  81
  82  static const struct of_device_id stm32_romem_of_match[] = {