git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From cb86630379c8f3432c916d62045b5176f17f4123 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sun, 16 Jul 2017 12:57:21 +0200
   4 Subject: [PATCH V2 6/8] MIPS: BCM63XX: move the HSSPI PLL HZ into its own
   5  clock
   6
   7 Split up the HSSPL clock into rate and a gate clock, to more closely
   8 match the actual hardware.
   9
  10 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  11 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  12 ---
  13  arch/mips/bcm63xx/clk.c | 10 ++++++++--
  14  1 file changed, 8 insertions(+), 2 deletions(-)
  15
  16 --- a/arch/mips/bcm63xx/clk.c
  17 +++ b/arch/mips/bcm63xx/clk.c
  18 @@ -247,6 +247,10 @@ static struct clk clk_hsspi = {
  19         .set    = hsspi_set,
  20  };
  21
  22 +/*
  23 + * HSSPI PLL
  24 + */
  25 +static struct clk clk_hsspi_pll;
  26
  27  /*
  28   * XTM clock
  29 @@ -373,6 +377,7 @@ static struct clk_lookup bcm6328_clks[]
  30         CLKDEV_INIT(NULL, "periph", &clk_periph),
  31         CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  32         CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  33 +       CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  34         /* gated clocks */
  35         CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  36         CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  37 @@ -440,6 +445,7 @@ static struct clk_lookup bcm6362_clks[]
  38         CLKDEV_INIT(NULL, "periph", &clk_periph),
  39         CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  40         CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  41 +       CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  42         /* gated clocks */
  43         CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  44         CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  45 @@ -474,7 +480,7 @@ static int __init bcm63xx_clk_init(void)
  46                 clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
  47                 break;
  48         case BCM6328_CPU_ID:
  49 -               clk_hsspi.rate = HSSPI_PLL_HZ_6328;
  50 +               clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
  51                 clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
  52                 break;
  53         case BCM6338_CPU_ID:
  54 @@ -490,7 +496,7 @@ static int __init bcm63xx_clk_init(void)
  55                 clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
  56                 break;
  57         case BCM6362_CPU_ID:
  58 -               clk_hsspi.rate = HSSPI_PLL_HZ_6362;
  59 +               clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
  60                 clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
  61                 break;
  62         case BCM6368_CPU_ID: