git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sat, 26 Feb 2022 14:52:32 +0100
   4 Subject: [PATCH 12/14] clk: qcom: gcc-ipq806x: add CryptoEngine clocks
   5
   6 Add missing CryptoEngine clocks and pll11 required clock.
   7
   8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
   9 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
  10 Tested-by: Jonathan McDowell <noodles@earth.li>
  11 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  12 Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com
  13 ---
  14  drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++
  15  1 file changed, 244 insertions(+)
  16
  17 --- a/drivers/clk/qcom/gcc-ipq806x.c
  18 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  19 @@ -256,6 +256,24 @@ static struct clk_pll pll18 = {
  20         },
  21  };
  22
  23 +static struct clk_pll pll11 = {
  24 +       .l_reg = 0x3184,
  25 +       .m_reg = 0x3188,
  26 +       .n_reg = 0x318c,
  27 +       .config_reg = 0x3194,
  28 +       .mode_reg = 0x3180,
  29 +       .status_reg = 0x3198,
  30 +       .status_bit = 16,
  31 +       .clkr.hw.init = &(struct clk_init_data){
  32 +               .name = "pll11",
  33 +               .parent_data = &(const struct clk_parent_data){
  34 +                       .fw_name = "pxo",
  35 +               },
  36 +               .num_parents = 1,
  37 +               .ops = &clk_pll_ops,
  38 +       },
  39 +};
  40 +
  41  enum {
  42         P_PXO,
  43         P_PLL8,
  44 @@ -264,6 +282,7 @@ enum {
  45         P_CXO,
  46         P_PLL14,
  47         P_PLL18,
  48 +       P_PLL11,
  49  };
  50
  51  static const struct parent_map gcc_pxo_pll8_map[] = {
  52 @@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_
  53         { .hw = &pll18.clkr.hw },
  54  };
  55
  56 +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
  57 +       { P_PXO, 0 },
  58 +       { P_PLL8, 4 },
  59 +       { P_PLL0, 2 },
  60 +       { P_PLL14, 5 },
  61 +       { P_PLL18, 1 },
  62 +       { P_PLL11, 3 },
  63 +};
  64 +
  65 +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
  66 +       { .fw_name = "pxo" },
  67 +       { .hw = &pll8_vote.hw },
  68 +       { .hw = &pll0_vote.hw },
  69 +       { .hw = &pll14.clkr.hw },
  70 +       { .hw = &pll18.clkr.hw },
  71 +       { .hw = &pll11.clkr.hw },
  72 +
  73 +};
  74 +
  75 +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
  76 +       { P_PXO, 0 },
  77 +       { P_PLL3, 6 },
  78 +       { P_PLL0, 2 },
  79 +       { P_PLL14, 5 },
  80 +       { P_PLL18, 1 },
  81 +       { P_PLL11, 3 },
  82 +};
  83 +
  84 +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
  85 +       { .fw_name = "pxo" },
  86 +       { .hw = &pll3.clkr.hw },
  87 +       { .hw = &pll0_vote.hw },
  88 +       { .hw = &pll14.clkr.hw },
  89 +       { .hw = &pll18.clkr.hw },
  90 +       { .hw = &pll11.clkr.hw },
  91 +
  92 +};
  93 +
  94  static struct freq_tbl clk_tbl_gsbi_uart[] = {
  95         {  1843200, P_PLL8, 2,  6, 625 },
  96         {  3686400, P_PLL8, 2, 12, 625 },
  97 @@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
  98         },
  99  };
 100
 101 +static const struct freq_tbl clk_tbl_ce5_core[] = {
 102 +       { 150000000, P_PLL3, 8, 1, 1 },
 103 +       { 213200000, P_PLL11, 5, 1, 1 },
 104 +       { }
 105 +};
 106 +
 107 +static struct clk_dyn_rcg ce5_core_src = {
 108 +       .ns_reg[0] = 0x36C4,
 109 +       .ns_reg[1] = 0x36C8,
 110 +       .bank_reg = 0x36C0,
 111 +       .s[0] = {
 112 +               .src_sel_shift = 0,
 113 +               .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
 114 +       },
 115 +       .s[1] = {
 116 +               .src_sel_shift = 0,
 117 +               .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
 118 +       },
 119 +       .p[0] = {
 120 +               .pre_div_shift = 3,
 121 +               .pre_div_width = 4,
 122 +       },
 123 +       .p[1] = {
 124 +               .pre_div_shift = 3,
 125 +               .pre_div_width = 4,
 126 +       },
 127 +       .mux_sel_bit = 0,
 128 +       .freq_tbl = clk_tbl_ce5_core,
 129 +       .clkr = {
 130 +               .enable_reg = 0x36C0,
 131 +               .enable_mask = BIT(1),
 132 +               .hw.init = &(struct clk_init_data){
 133 +                       .name = "ce5_core_src",
 134 +                       .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
 135 +                       .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
 136 +                       .ops = &clk_dyn_rcg_ops,
 137 +               },
 138 +       },
 139 +};
 140 +
 141 +static struct clk_branch ce5_core_clk = {
 142 +       .halt_reg = 0x2FDC,
 143 +       .halt_bit = 5,
 144 +       .hwcg_reg = 0x36CC,
 145 +       .hwcg_bit = 6,
 146 +       .clkr = {
 147 +               .enable_reg = 0x36CC,
 148 +               .enable_mask = BIT(4),
 149 +               .hw.init = &(struct clk_init_data){
 150 +                       .name = "ce5_core_clk",
 151 +                       .parent_hws = (const struct clk_hw*[]){
 152 +                               &ce5_core_src.clkr.hw,
 153 +                       },
 154 +                       .num_parents = 1,
 155 +                       .ops = &clk_branch_ops,
 156 +                       .flags = CLK_SET_RATE_PARENT,
 157 +               },
 158 +       },
 159 +};
 160 +
 161 +static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
 162 +       { 160000000, P_PLL0, 5, 1, 1 },
 163 +       { 213200000, P_PLL11, 5, 1, 1 },
 164 +       { }
 165 +};
 166 +
 167 +static struct clk_dyn_rcg ce5_a_clk_src = {
 168 +       .ns_reg[0] = 0x3d84,
 169 +       .ns_reg[1] = 0x3d88,
 170 +       .bank_reg = 0x3d80,
 171 +       .s[0] = {
 172 +               .src_sel_shift = 0,
 173 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 174 +       },
 175 +       .s[1] = {
 176 +               .src_sel_shift = 0,
 177 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 178 +       },
 179 +       .p[0] = {
 180 +               .pre_div_shift = 3,
 181 +               .pre_div_width = 4,
 182 +       },
 183 +       .p[1] = {
 184 +               .pre_div_shift = 3,
 185 +               .pre_div_width = 4,
 186 +       },
 187 +       .mux_sel_bit = 0,
 188 +       .freq_tbl = clk_tbl_ce5_a_clk,
 189 +       .clkr = {
 190 +               .enable_reg = 0x3d80,
 191 +               .enable_mask = BIT(1),
 192 +               .hw.init = &(struct clk_init_data){
 193 +                       .name = "ce5_a_clk_src",
 194 +                       .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
 195 +                       .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
 196 +                       .ops = &clk_dyn_rcg_ops,
 197 +               },
 198 +       },
 199 +};
 200 +
 201 +static struct clk_branch ce5_a_clk = {
 202 +       .halt_reg = 0x3c20,
 203 +       .halt_bit = 12,
 204 +       .hwcg_reg = 0x3d8c,
 205 +       .hwcg_bit = 6,
 206 +       .clkr = {
 207 +               .enable_reg = 0x3d8c,
 208 +               .enable_mask = BIT(4),
 209 +               .hw.init = &(struct clk_init_data){
 210 +                       .name = "ce5_a_clk",
 211 +                       .parent_hws = (const struct clk_hw*[]){
 212 +                               &ce5_a_clk_src.clkr.hw,
 213 +                       },
 214 +                       .num_parents = 1,
 215 +                       .ops = &clk_branch_ops,
 216 +                       .flags = CLK_SET_RATE_PARENT,
 217 +               },
 218 +       },
 219 +};
 220 +
 221 +static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
 222 +       { 160000000, P_PLL0, 5, 1, 1 },
 223 +       { 213200000, P_PLL11, 5, 1, 1 },
 224 +       { }
 225 +};
 226 +
 227 +static struct clk_dyn_rcg ce5_h_clk_src = {
 228 +       .ns_reg[0] = 0x3c64,
 229 +       .ns_reg[1] = 0x3c68,
 230 +       .bank_reg = 0x3c60,
 231 +       .s[0] = {
 232 +               .src_sel_shift = 0,
 233 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 234 +       },
 235 +       .s[1] = {
 236 +               .src_sel_shift = 0,
 237 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 238 +       },
 239 +       .p[0] = {
 240 +               .pre_div_shift = 3,
 241 +               .pre_div_width = 4,
 242 +       },
 243 +       .p[1] = {
 244 +               .pre_div_shift = 3,
 245 +               .pre_div_width = 4,
 246 +       },
 247 +       .mux_sel_bit = 0,
 248 +       .freq_tbl = clk_tbl_ce5_h_clk,
 249 +       .clkr = {
 250 +               .enable_reg = 0x3c60,
 251 +               .enable_mask = BIT(1),
 252 +               .hw.init = &(struct clk_init_data){
 253 +                       .name = "ce5_h_clk_src",
 254 +                       .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
 255 +                       .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
 256 +                       .ops = &clk_dyn_rcg_ops,
 257 +               },
 258 +       },
 259 +};
 260 +
 261 +static struct clk_branch ce5_h_clk = {
 262 +       .halt_reg = 0x3c20,
 263 +       .halt_bit = 11,
 264 +       .hwcg_reg = 0x3c6c,
 265 +       .hwcg_bit = 6,
 266 +       .clkr = {
 267 +               .enable_reg = 0x3c6c,
 268 +               .enable_mask = BIT(4),
 269 +               .hw.init = &(struct clk_init_data){
 270 +                       .name = "ce5_h_clk",
 271 +                       .parent_hws = (const struct clk_hw*[]){
 272 +                               &ce5_h_clk_src.clkr.hw,
 273 +                       },
 274 +                       .num_parents = 1,
 275 +                       .ops = &clk_branch_ops,
 276 +                       .flags = CLK_SET_RATE_PARENT,
 277 +               },
 278 +       },
 279 +};
 280 +
 281  static struct clk_regmap *gcc_ipq806x_clks[] = {
 282         [PLL0] = &pll0.clkr,
 283         [PLL0_VOTE] = &pll0_vote,
 284 @@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_cl
 285         [PLL4_VOTE] = &pll4_vote,
 286         [PLL8] = &pll8.clkr,
 287         [PLL8_VOTE] = &pll8_vote,
 288 +       [PLL11] = &pll11.clkr,
 289         [PLL14] = &pll14.clkr,
 290         [PLL14_VOTE] = &pll14_vote,
 291         [PLL18] = &pll18.clkr,
 292 @@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_cl
 293         [PLL9] = &hfpll0.clkr,
 294         [PLL10] = &hfpll1.clkr,
 295         [PLL12] = &hfpll_l2.clkr,
 296 +       [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
 297 +       [CE5_A_CLK] = &ce5_a_clk.clkr,
 298 +       [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
 299 +       [CE5_H_CLK] = &ce5_h_clk.clkr,
 300 +       [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
 301 +       [CE5_CORE_CLK] = &ce5_core_clk.clkr,
 302  };
 303
 304  static const struct qcom_reset_map gcc_ipq806x_resets[] = {