git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
   2 From: Sam Shih <sam.shih@mediatek.com>
   3 Date: Sat, 8 Oct 2022 18:48:06 +0200
   4 Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
   5  separately
   6
   7 Some mt7986 boards use uart rts/cts pins as gpio,
   8 This patch allows to change rts/cts to gpio mode, but keep
   9 rx/tx as UART function.
  10
  11 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
  12 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
  13 Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de
  14 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  15 ---
  16  drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
  17  1 file changed, 25 insertions(+), 7 deletions(-)
  18
  19 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
  20 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
  21 @@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
  22  static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
  23  static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
  24
  25 -static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
  26 -static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
  27 +static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
  28 +static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
  29
  30 -static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
  31 -static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
  32 +static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
  33 +static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
  34 +
  35 +static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
  36 +static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
  37 +
  38 +static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
  39 +static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
  40
  41  static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
  42  static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
  43 @@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
  44  static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
  45  static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
  46
  47 +static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
  48 +static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
  49 +
  50 +static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
  51 +static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
  52 +
  53  static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
  54  static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
  55
  56 @@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
  57         PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
  58         PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
  59         PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
  60 +       PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
  61 +       PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
  62         PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
  63         PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
  64         PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
  65 @@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
  66         PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
  67         PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
  68         PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
  69 -       PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
  70 -       PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
  71 +       PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
  72 +       PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
  73 +       PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
  74 +       PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
  75         PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
  76         PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
  77         PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
  78 @@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
  79  static const char *mt7986_spi_groups[] = {
  80         "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
  81  static const char *mt7986_uart_groups[] = {
  82 -       "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
  83 +       "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
  84 +       "uart1_2_rx_tx", "uart1_2_cts_rts",
  85 +       "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
  86         "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
  87  };
  88  static const char *mt7986_wdt_groups[] = { "watchdog", };