git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From f9ec5723c3dbfcede9c7b0dcdf85e401ce16316c Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Sat, 23 Jul 2022 16:29:29 +0200
   4 Subject: [PATCH 1/5] net: ethernet: stmicro: stmmac: move queue reset to
   5  dedicated functions
   6
   7 Move queue reset to dedicated functions. This aside from a simple
   8 cleanup is also required to allocate a dma conf without resetting the tx
   9 queue while the device is temporarily detached as now the reset is not
  10 part of the dma init function and can be done later in the code flow.
  11
  12 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  14 ---
  15  .../net/ethernet/stmicro/stmmac/stmmac_main.c | 59 ++++++++++---------
  16  1 file changed, 31 insertions(+), 28 deletions(-)
  17
  18 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
  19 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
  20 @@ -130,6 +130,9 @@ static irqreturn_t stmmac_mac_interrupt(
  21  static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
  22  static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
  23  static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
  24 +static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue);
  25 +static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue);
  26 +static void stmmac_reset_queues_param(struct stmmac_priv *priv);
  27  static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
  28  static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
  29
  30 @@ -1713,9 +1716,6 @@ static int __init_dma_rx_desc_rings(stru
  31                         return -ENOMEM;
  32         }
  33
  34 -       rx_q->cur_rx = 0;
  35 -       rx_q->dirty_rx = 0;
  36 -
  37         /* Setup the chained descriptor addresses */
  38         if (priv->mode == STMMAC_CHAIN_MODE) {
  39                 if (priv->extend_desc)
  40 @@ -1821,12 +1821,6 @@ static int __init_dma_tx_desc_rings(stru
  41                 tx_q->tx_skbuff[i] = NULL;
  42         }
  43
  44 -       tx_q->dirty_tx = 0;
  45 -       tx_q->cur_tx = 0;
  46 -       tx_q->mss = 0;
  47 -
  48 -       netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
  49 -
  50         return 0;
  51  }
  52
  53 @@ -2695,10 +2689,7 @@ static void stmmac_tx_err(struct stmmac_
  54         stmmac_stop_tx_dma(priv, chan);
  55         dma_free_tx_skbufs(priv, chan);
  56         stmmac_clear_tx_descriptors(priv, chan);
  57 -       tx_q->dirty_tx = 0;
  58 -       tx_q->cur_tx = 0;
  59 -       tx_q->mss = 0;
  60 -       netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
  61 +       stmmac_reset_tx_queue(priv, chan);
  62         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  63                             tx_q->dma_tx_phy, chan);
  64         stmmac_start_tx_dma(priv, chan);
  65 @@ -3783,6 +3774,8 @@ static int stmmac_open(struct net_device
  66                 }
  67         }
  68
  69 +       stmmac_reset_queues_param(priv);
  70 +
  71         ret = stmmac_hw_setup(dev, true);
  72         if (ret < 0) {
  73                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
  74 @@ -6412,6 +6405,7 @@ void stmmac_enable_rx_queue(struct stmma
  75                 return;
  76         }
  77
  78 +       stmmac_reset_rx_queue(priv, queue);
  79         stmmac_clear_rx_descriptors(priv, queue);
  80
  81         stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  82 @@ -6473,6 +6467,7 @@ void stmmac_enable_tx_queue(struct stmma
  83                 return;
  84         }
  85
  86 +       stmmac_reset_tx_queue(priv, queue);
  87         stmmac_clear_tx_descriptors(priv, queue);
  88
  89         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  90 @@ -7400,6 +7395,25 @@ int stmmac_suspend(struct device *dev)
  91  }
  92  EXPORT_SYMBOL_GPL(stmmac_suspend);
  93
  94 +static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
  95 +{
  96 +       struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
  97 +
  98 +       rx_q->cur_rx = 0;
  99 +       rx_q->dirty_rx = 0;
 100 +}
 101 +
 102 +static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
 103 +{
 104 +       struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 105 +
 106 +       tx_q->cur_tx = 0;
 107 +       tx_q->dirty_tx = 0;
 108 +       tx_q->mss = 0;
 109 +
 110 +       netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
 111 +}
 112 +
 113  /**
 114   * stmmac_reset_queues_param - reset queue parameters
 115   * @priv: device pointer
 116 @@ -7410,22 +7424,11 @@ static void stmmac_reset_queues_param(st
 117         u32 tx_cnt = priv->plat->tx_queues_to_use;
 118         u32 queue;
 119
 120 -       for (queue = 0; queue < rx_cnt; queue++) {
 121 -               struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 122 +       for (queue = 0; queue < rx_cnt; queue++)
 123 +               stmmac_reset_rx_queue(priv, queue);
 124
 125 -               rx_q->cur_rx = 0;
 126 -               rx_q->dirty_rx = 0;
 127 -       }
 128 -
 129 -       for (queue = 0; queue < tx_cnt; queue++) {
 130 -               struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 131 -
 132 -               tx_q->cur_tx = 0;
 133 -               tx_q->dirty_tx = 0;
 134 -               tx_q->mss = 0;
 135 -
 136 -               netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
 137 -       }
 138 +       for (queue = 0; queue < tx_cnt; queue++)
 139 +               stmmac_reset_tx_queue(priv, queue);
 140  }
 141
 142  /**