git.openwrt.org Git - openwrt/staging/aparcar.git/blob

   1 From 1b47b98acce2db0da632d056821420b33205b8b2 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Tue, 19 Apr 2016 08:56:46 +0200
   4 Subject: [PATCH] ARM: BCM5301X: Add DT entry for SPI controller and NOR flash
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Controller is present on every BCM4708* board but only few devices have
  10 serial flash attached so mark it as disabled by default.
  11
  12 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  13 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  14 ---
  15
  16 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
  17 +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
  18 @@ -59,3 +59,7 @@
  19  &uart0 {
  20         status = "okay";
  21  };
  22 +
  23 +&spi_nor {
  24 +       status = "okay";
  25 +};
  26 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
  27 +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
  28 @@ -122,3 +122,7 @@
  29  &uart0 {
  30         status = "okay";
  31  };
  32 +
  33 +&spi_nor {
  34 +       status = "okay";
  35 +};
  36 --- a/arch/arm/boot/dts/bcm5301x.dtsi
  37 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  38 @@ -225,6 +225,20 @@
  39                         #address-cells = <1>;
  40                         #size-cells = <1>;
  41                 };
  42 +
  43 +               spi@29000 {
  44 +                       reg = <0x00029000 0x1000>;
  45 +                       #address-cells = <1>;
  46 +                       #size-cells = <0>;
  47 +
  48 +                       spi_nor: spi-nor@0 {
  49 +                               compatible = "jedec,spi-nor";
  50 +                               reg = <0>;
  51 +                               spi-max-frequency = <20000000>;
  52 +                               linux,part-probe = "ofpart", "bcm47xxpart";
  53 +                               status = "disabled";
  54 +                       };
  55 +               };
  56         };
  57
  58         lcpll0: lcpll0@1800c100 {