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1 From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001
2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
3 Date: Fri, 11 Nov 2022 10:41:06 +0100
4 Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time
5 configuration
6
7 The External Interrupt Controller (EINTC) on all of the supported
8 MediaTek SoCs does support input debouncing, but not all of them
9 index the debounce time values (DBNC_SETTING registers) the same way.
10
11 Before this change, in some cases, as an example, requesting a debounce
12 time of 16 milliseconds would mistakenly set the relative DBNC_SETTING
13 register to 0x2, resulting in a way shorter debounce time of 500uS.
14
15 To fix the aforementioned issue, define three different debounce_time
16 arrays, reflecting the correct register index for each value and for
17 each register index variant, and make sure that each SoC pinctrl
18 driver uses the right one.
19
20 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
21 Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com
22 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
23 ---
24 drivers/pinctrl/mediatek/mtk-eint.c | 31 +++++++++++++++++++----
25 drivers/pinctrl/mediatek/mtk-eint.h | 6 +++++
26 drivers/pinctrl/mediatek/pinctrl-mt2701.c | 1 +
27 drivers/pinctrl/mediatek/pinctrl-mt2712.c | 1 +
28 drivers/pinctrl/mediatek/pinctrl-mt6765.c | 1 +
29 drivers/pinctrl/mediatek/pinctrl-mt6779.c | 1 +
30 drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1 +
31 drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1 +
32 drivers/pinctrl/mediatek/pinctrl-mt7629.c | 1 +
33 drivers/pinctrl/mediatek/pinctrl-mt8127.c | 1 +
34 drivers/pinctrl/mediatek/pinctrl-mt8135.c | 1 +
35 drivers/pinctrl/mediatek/pinctrl-mt8167.c | 1 +
36 drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 +
37 drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 +
38 drivers/pinctrl/mediatek/pinctrl-mt8192.c | 1 +
39 drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 +
40 drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
41 drivers/pinctrl/mediatek/pinctrl-mt8516.c | 1 +
42 22 files changed, 53 insertions(+), 5 deletions(-)
43
44 --- a/drivers/pinctrl/mediatek/mtk-eint.c
45 +++ b/drivers/pinctrl/mediatek/mtk-eint.c
46 @@ -24,6 +24,7 @@
47 #define MTK_EINT_EDGE_SENSITIVE 0
48 #define MTK_EINT_LEVEL_SENSITIVE 1
49 #define MTK_EINT_DBNC_SET_DBNC_BITS 4
50 +#define MTK_EINT_DBNC_MAX 16
51 #define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
52 #define MTK_EINT_DBNC_SET_EN (0x1 << 0)
53
54 @@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge
55 .dbnc_clr = 0x700,
56 };
57
58 +const unsigned int debounce_time_mt2701[] = {
59 + 500, 1000, 16000, 32000, 64000, 128000, 256000, 0
60 +};
61 +
62 +const unsigned int debounce_time_mt6765[] = {
63 + 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
64 +};
65 +
66 +const unsigned int debounce_time_mt6795[] = {
67 + 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
68 +};
69 +
70 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
71 unsigned int eint_num,
72 unsigned int offset)
73 @@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein
74 int virq, eint_offset;
75 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
76 dbnc;
77 - static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
78 - 64000, 128000, 256000};
79 struct irq_data *d;
80
81 + if (!eint->hw->db_time)
82 + return -EOPNOTSUPP;
83 +
84 virq = irq_find_mapping(eint->domain, eint_num);
85 eint_offset = (eint_num % 4) * 8;
86 d = irq_get_irq_data(virq);
87 @@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein
88 if (!mtk_eint_can_en_debounce(eint, eint_num))
89 return -EINVAL;
90
91 - dbnc = ARRAY_SIZE(debounce_time);
92 - for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
93 - if (debounce <= debounce_time[i]) {
94 + dbnc = eint->num_db_time;
95 + for (i = 0; i < eint->num_db_time; i++) {
96 + if (debounce <= eint->hw->db_time[i]) {
97 dbnc = i;
98 break;
99 }
100 @@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei
101 if (!eint->domain)
102 return -ENOMEM;
103
104 + if (eint->hw->db_time) {
105 + for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
106 + if (eint->hw->db_time[i] == 0)
107 + break;
108 + eint->num_db_time = i;
109 + }
110 +
111 mtk_eint_hw_init(eint);
112 for (i = 0; i < eint->hw->ap_num; i++) {
113 int virq = irq_create_mapping(eint->domain, i);
114 --- a/drivers/pinctrl/mediatek/mtk-eint.h
115 +++ b/drivers/pinctrl/mediatek/mtk-eint.h
116 @@ -37,8 +37,13 @@ struct mtk_eint_hw {
117 u8 ports;
118 unsigned int ap_num;
119 unsigned int db_cnt;
120 + const unsigned int *db_time;
121 };
122
123 +extern const unsigned int debounce_time_mt2701[];
124 +extern const unsigned int debounce_time_mt6765[];
125 +extern const unsigned int debounce_time_mt6795[];
126 +
127 struct mtk_eint;
128
129 struct mtk_eint_xt {
130 @@ -62,6 +67,7 @@ struct mtk_eint {
131 /* Used to fit into various EINT device */
132 const struct mtk_eint_hw *hw;
133 const struct mtk_eint_regs *regs;
134 + u16 num_db_time;
135
136 /* Used to fit into various pinctrl device */
137 void *pctl;
138 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
139 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
140 @@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata
141 .ports = 6,
142 .ap_num = 169,
143 .db_cnt = 16,
144 + .db_time = debounce_time_mt2701,
145 },
146 };
147
148 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
149 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
150 @@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata
151 .ports = 8,
152 .ap_num = 229,
153 .db_cnt = 40,
154 + .db_time = debounce_time_mt2701,
155 },
156 };
157
158 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c
159 +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
160 @@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e
161 .ports = 6,
162 .ap_num = 160,
163 .db_cnt = 13,
164 + .db_time = debounce_time_mt6765,
165 };
166
167 static const struct mtk_pin_soc mt6765_data = {
168 --- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
169 +++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
170 @@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e
171 .ports = 6,
172 .ap_num = 195,
173 .db_cnt = 13,
174 + .db_time = debounce_time_mt2701,
175 };
176
177 static const struct mtk_pin_soc mt6779_data = {
178 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
179 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
180 @@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e
181 .ports = 7,
182 .ap_num = ARRAY_SIZE(mt7622_pins),
183 .db_cnt = 20,
184 + .db_time = debounce_time_mt6765,
185 };
186
187 static const struct mtk_pin_soc mt7622_data = {
188 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
189 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
190 @@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e
191 .ports = 6,
192 .ap_num = 169,
193 .db_cnt = 20,
194 + .db_time = debounce_time_mt2701,
195 };
196
197 static struct mtk_pin_soc mt7623_data = {
198 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
199 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
200 @@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e
201 .ports = 7,
202 .ap_num = ARRAY_SIZE(mt7629_pins),
203 .db_cnt = 16,
204 + .db_time = debounce_time_mt2701,
205 };
206
207 static struct mtk_pin_soc mt7629_data = {
208 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c
209 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
210 @@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata
211 .ports = 6,
212 .ap_num = 143,
213 .db_cnt = 16,
214 + .db_time = debounce_time_mt2701,
215 },
216 };
217
218 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
219 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
220 @@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata
221 .ports = 6,
222 .ap_num = 192,
223 .db_cnt = 16,
224 + .db_time = debounce_time_mt2701,
225 },
226 };
227
228 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
229 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
230 @@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
231 .ports = 6,
232 .ap_num = 169,
233 .db_cnt = 64,
234 + .db_time = debounce_time_mt6795,
235 },
236 };
237
238 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
239 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
240 @@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata
241 .ports = 6,
242 .ap_num = 224,
243 .db_cnt = 16,
244 + .db_time = debounce_time_mt2701,
245 },
246 };
247
248 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
249 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
250 @@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e
251 .ports = 6,
252 .ap_num = 212,
253 .db_cnt = 13,
254 + .db_time = debounce_time_mt6765,
255 };
256
257 static const struct mtk_pin_soc mt8183_data = {
258 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c
259 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c
260 @@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e
261 .ports = 7,
262 .ap_num = 224,
263 .db_cnt = 32,
264 + .db_time = debounce_time_mt6765,
265 };
266
267 static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = {
268 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
269 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
270 @@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e
271 .ports = 7,
272 .ap_num = 225,
273 .db_cnt = 32,
274 + .db_time = debounce_time_mt6765,
275 };
276
277 static const struct mtk_pin_soc mt8195_data = {
278 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
279 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
280 @@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata
281 .ports = 5,
282 .ap_num = 160,
283 .db_cnt = 160,
284 + .db_time = debounce_time_mt6765,
285 },
286 };
287
288 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
289 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
290 @@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
291 .ports = 6,
292 .ap_num = 169,
293 .db_cnt = 64,
294 + .db_time = debounce_time_mt6795,
295 },
296 };
297
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