projects / openwrt / staging / lynxis.git / blob
? search:


4a1d782831df9374c6510fd37688d29eea975fae
[openwrt/staging/lynxis.git] /
1 From a8cc5cde3eb83074ccf21380432e8ef9e4d72347 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Wed, 12 Dec 2018 15:51:48 -0800
4 Subject: [PATCH 554/782] soc: bcm: bcm2835-pm: Add support for power domains
5 under a new binding.
6
7 This provides a free software alternative to raspberrypi-power.c's
8 firmware calls to manage power domains. It also exposes a reset line,
9 where previously the vc4 driver had to try to force power off the
10 domain in order to trigger a reset.
11
12 Signed-off-by: Eric Anholt <eric@anholt.net>
13 Acked-by: Rob Herring <robh@kernel.org>
14 Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
15 Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
16 (cherry picked from commit 670c672608a1ffcbc7ac0f872734843593bb8b15)
17 ---
18 drivers/mfd/bcm2835-pm.c | 36 +-
19 drivers/soc/bcm/Kconfig | 11 +
20 drivers/soc/bcm/Makefile | 1 +
21 drivers/soc/bcm/bcm2835-power.c | 661 +++++++++++++++++++++++++++
22 include/dt-bindings/soc/bcm2835-pm.h | 28 ++
23 include/linux/mfd/bcm2835-pm.h | 1 +
24 6 files changed, 734 insertions(+), 4 deletions(-)
25 create mode 100644 drivers/soc/bcm/bcm2835-power.c
26 create mode 100644 include/dt-bindings/soc/bcm2835-pm.h
27
28 --- a/drivers/mfd/bcm2835-pm.c
29 +++ b/drivers/mfd/bcm2835-pm.c
30 @@ -3,7 +3,7 @@
31 * PM MFD driver for Broadcom BCM2835
32 *
33 * This driver binds to the PM block and creates the MFD device for
34 - * the WDT driver.
35 + * the WDT and power drivers.
36 */
37
38 #include <linux/delay.h>
39 @@ -21,11 +21,16 @@ static const struct mfd_cell bcm2835_pm_
40 { .name = "bcm2835-wdt" },
41 };
42
43 +static const struct mfd_cell bcm2835_power_devs[] = {
44 + { .name = "bcm2835-power" },
45 +};
46 +
47 static int bcm2835_pm_probe(struct platform_device *pdev)
48 {
49 struct resource *res;
50 struct device *dev = &pdev->dev;
51 struct bcm2835_pm *pm;
52 + int ret;
53
54 pm = devm_kzalloc(dev, sizeof(*pm), GFP_KERNEL);
55 if (!pm)
56 @@ -39,13 +44,36 @@ static int bcm2835_pm_probe(struct platf
57 if (IS_ERR(pm->base))
58 return PTR_ERR(pm->base);
59
60 - return devm_mfd_add_devices(dev, -1,
61 - bcm2835_pm_devs, ARRAY_SIZE(bcm2835_pm_devs),
62 - NULL, 0, NULL);
63 + ret = devm_mfd_add_devices(dev, -1,
64 + bcm2835_pm_devs, ARRAY_SIZE(bcm2835_pm_devs),
65 + NULL, 0, NULL);
66 + if (ret)
67 + return ret;
68 +
69 + /* We'll use the presence of the AXI ASB regs in the
70 + * bcm2835-pm binding as the key for whether we can reference
71 + * the full PM register range and support power domains.
72 + */
73 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
74 + if (res) {
75 + pm->asb = devm_ioremap_resource(dev, res);
76 + if (IS_ERR(pm->asb))
77 + return PTR_ERR(pm->asb);
78 +
79 + ret = devm_mfd_add_devices(dev, -1,
80 + bcm2835_power_devs,
81 + ARRAY_SIZE(bcm2835_power_devs),
82 + NULL, 0, NULL);
83 + if (ret)
84 + return ret;
85 + }
86 +
87 + return 0;
88 }
89
90 static const struct of_device_id bcm2835_pm_of_match[] = {
91 { .compatible = "brcm,bcm2835-pm-wdt", },
92 + { .compatible = "brcm,bcm2835-pm", },
93 {},
94 };
95 MODULE_DEVICE_TABLE(of, bcm2835_pm_of_match);
96 --- a/drivers/soc/bcm/Kconfig
97 +++ b/drivers/soc/bcm/Kconfig
98 @@ -1,5 +1,16 @@
99 menu "Broadcom SoC drivers"
100
101 +config BCM2835_POWER
102 + bool "BCM2835 power domain driver"
103 + depends on ARCH_BCM2835 || (COMPILE_TEST && OF)
104 + select PM_GENERIC_DOMAINS if PM
105 + select RESET_CONTROLLER
106 + help
107 + This enables support for the BCM2835 power domains and reset
108 + controller. Any usage of power domains by the Raspberry Pi
109 + firmware means that Linux usage of the same power domain
110 + must be accessed using the RASPBERRYPI_POWER driver
111 +
112 config RASPBERRYPI_POWER
113 bool "Raspberry Pi power domain driver"
114 depends on ARCH_BCM2835 || (COMPILE_TEST && OF)
115 --- a/drivers/soc/bcm/Makefile
116 +++ b/drivers/soc/bcm/Makefile
117 @@ -1,2 +1,3 @@
118 +obj-$(CONFIG_BCM2835_POWER) += bcm2835-power.o
119 obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o
120 obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/
121 --- /dev/null
122 +++ b/drivers/soc/bcm/bcm2835-power.c
123 @@ -0,0 +1,661 @@
124 +// SPDX-License-Identifier: GPL-2.0+
125 +/*
126 + * Power domain driver for Broadcom BCM2835
127 + *
128 + * Copyright (C) 2018 Broadcom
129 + */
130 +
131 +#include <dt-bindings/soc/bcm2835-pm.h>
132 +#include <linux/clk.h>
133 +#include <linux/delay.h>
134 +#include <linux/io.h>
135 +#include <linux/mfd/bcm2835-pm.h>
136 +#include <linux/module.h>
137 +#include <linux/platform_device.h>
138 +#include <linux/pm_domain.h>
139 +#include <linux/reset-controller.h>
140 +#include <linux/types.h>
141 +
142 +#define PM_GNRIC 0x00
143 +#define PM_AUDIO 0x04
144 +#define PM_STATUS 0x18
145 +#define PM_RSTC 0x1c
146 +#define PM_RSTS 0x20
147 +#define PM_WDOG 0x24
148 +#define PM_PADS0 0x28
149 +#define PM_PADS2 0x2c
150 +#define PM_PADS3 0x30
151 +#define PM_PADS4 0x34
152 +#define PM_PADS5 0x38
153 +#define PM_PADS6 0x3c
154 +#define PM_CAM0 0x44
155 +#define PM_CAM0_LDOHPEN BIT(2)
156 +#define PM_CAM0_LDOLPEN BIT(1)
157 +#define PM_CAM0_CTRLEN BIT(0)
158 +
159 +#define PM_CAM1 0x48
160 +#define PM_CAM1_LDOHPEN BIT(2)
161 +#define PM_CAM1_LDOLPEN BIT(1)
162 +#define PM_CAM1_CTRLEN BIT(0)
163 +
164 +#define PM_CCP2TX 0x4c
165 +#define PM_CCP2TX_LDOEN BIT(1)
166 +#define PM_CCP2TX_CTRLEN BIT(0)
167 +
168 +#define PM_DSI0 0x50
169 +#define PM_DSI0_LDOHPEN BIT(2)
170 +#define PM_DSI0_LDOLPEN BIT(1)
171 +#define PM_DSI0_CTRLEN BIT(0)
172 +
173 +#define PM_DSI1 0x54
174 +#define PM_DSI1_LDOHPEN BIT(2)
175 +#define PM_DSI1_LDOLPEN BIT(1)
176 +#define PM_DSI1_CTRLEN BIT(0)
177 +
178 +#define PM_HDMI 0x58
179 +#define PM_HDMI_RSTDR BIT(19)
180 +#define PM_HDMI_LDOPD BIT(1)
181 +#define PM_HDMI_CTRLEN BIT(0)
182 +
183 +#define PM_USB 0x5c
184 +/* The power gates must be enabled with this bit before enabling the LDO in the
185 + * USB block.
186 + */
187 +#define PM_USB_CTRLEN BIT(0)
188 +
189 +#define PM_PXLDO 0x60
190 +#define PM_PXBG 0x64
191 +#define PM_DFT 0x68
192 +#define PM_SMPS 0x6c
193 +#define PM_XOSC 0x70
194 +#define PM_SPAREW 0x74
195 +#define PM_SPARER 0x78
196 +#define PM_AVS_RSTDR 0x7c
197 +#define PM_AVS_STAT 0x80
198 +#define PM_AVS_EVENT 0x84
199 +#define PM_AVS_INTEN 0x88
200 +#define PM_DUMMY 0xfc
201 +
202 +#define PM_IMAGE 0x108
203 +#define PM_GRAFX 0x10c
204 +#define PM_PROC 0x110
205 +#define PM_ENAB BIT(12)
206 +#define PM_ISPRSTN BIT(8)
207 +#define PM_H264RSTN BIT(7)
208 +#define PM_PERIRSTN BIT(6)
209 +#define PM_V3DRSTN BIT(6)
210 +#define PM_ISFUNC BIT(5)
211 +#define PM_MRDONE BIT(4)
212 +#define PM_MEMREP BIT(3)
213 +#define PM_ISPOW BIT(2)
214 +#define PM_POWOK BIT(1)
215 +#define PM_POWUP BIT(0)
216 +#define PM_INRUSH_SHIFT 13
217 +#define PM_INRUSH_3_5_MA 0
218 +#define PM_INRUSH_5_MA 1
219 +#define PM_INRUSH_10_MA 2
220 +#define PM_INRUSH_20_MA 3
221 +#define PM_INRUSH_MASK (3 << PM_INRUSH_SHIFT)
222 +
223 +#define PM_PASSWORD 0x5a000000
224 +
225 +#define PM_WDOG_TIME_SET 0x000fffff
226 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
227 +#define PM_RSTS_HADWRH_SET 0x00000040
228 +#define PM_RSTC_WRCFG_SET 0x00000030
229 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
230 +#define PM_RSTC_RESET 0x00000102
231 +
232 +#define PM_READ(reg) readl(power->base + (reg))
233 +#define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
234 +
235 +#define ASB_BRDG_VERSION 0x00
236 +#define ASB_CPR_CTRL 0x04
237 +
238 +#define ASB_V3D_S_CTRL 0x08
239 +#define ASB_V3D_M_CTRL 0x0c
240 +#define ASB_ISP_S_CTRL 0x10
241 +#define ASB_ISP_M_CTRL 0x14
242 +#define ASB_H264_S_CTRL 0x18
243 +#define ASB_H264_M_CTRL 0x1c
244 +
245 +#define ASB_REQ_STOP BIT(0)
246 +#define ASB_ACK BIT(1)
247 +#define ASB_EMPTY BIT(2)
248 +#define ASB_FULL BIT(3)
249 +
250 +#define ASB_AXI_BRDG_ID 0x20
251 +
252 +#define ASB_READ(reg) readl(power->asb + (reg))
253 +#define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg))
254 +
255 +struct bcm2835_power_domain {
256 + struct generic_pm_domain base;
257 + struct bcm2835_power *power;
258 + u32 domain;
259 + struct clk *clk;
260 +};
261 +
262 +struct bcm2835_power {
263 + struct device *dev;
264 + /* PM registers. */
265 + void __iomem *base;
266 + /* AXI Async bridge registers. */
267 + void __iomem *asb;
268 +
269 + struct genpd_onecell_data pd_xlate;
270 + struct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT];
271 + struct reset_controller_dev reset;
272 +};
273 +
274 +static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg)
275 +{
276 + u64 start = ktime_get_ns();
277 +
278 + /* Enable the module's async AXI bridges. */
279 + ASB_WRITE(reg, ASB_READ(reg) & ~ASB_REQ_STOP);
280 + while (ASB_READ(reg) & ASB_ACK) {
281 + cpu_relax();
282 + if (ktime_get_ns() - start >= 1000)
283 + return -ETIMEDOUT;
284 + }
285 +
286 + return 0;
287 +}
288 +
289 +static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg)
290 +{
291 + u64 start = ktime_get_ns();
292 +
293 + /* Enable the module's async AXI bridges. */
294 + ASB_WRITE(reg, ASB_READ(reg) | ASB_REQ_STOP);
295 + while (!(ASB_READ(reg) & ASB_ACK)) {
296 + cpu_relax();
297 + if (ktime_get_ns() - start >= 1000)
298 + return -ETIMEDOUT;
299 + }
300 +
301 + return 0;
302 +}
303 +
304 +static int bcm2835_power_power_off(struct bcm2835_power_domain *pd, u32 pm_reg)
305 +{
306 + struct bcm2835_power *power = pd->power;
307 +
308 + /* Enable functional isolation */
309 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC);
310 +
311 + /* Enable electrical isolation */
312 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
313 +
314 + /* Open the power switches. */
315 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_POWUP);
316 +
317 + return 0;
318 +}
319 +
320 +static int bcm2835_power_power_on(struct bcm2835_power_domain *pd, u32 pm_reg)
321 +{
322 + struct bcm2835_power *power = pd->power;
323 + struct device *dev = power->dev;
324 + u64 start;
325 + int ret;
326 + int inrush;
327 + bool powok;
328 +
329 + /* If it was already powered on by the fw, leave it that way. */
330 + if (PM_READ(pm_reg) & PM_POWUP)
331 + return 0;
332 +
333 + /* Enable power. Allowing too much current at once may result
334 + * in POWOK never getting set, so start low and ramp it up as
335 + * necessary to succeed.
336 + */
337 + powok = false;
338 + for (inrush = PM_INRUSH_3_5_MA; inrush <= PM_INRUSH_20_MA; inrush++) {
339 + PM_WRITE(pm_reg,
340 + (PM_READ(pm_reg) & ~PM_INRUSH_MASK) |
341 + (inrush << PM_INRUSH_SHIFT) |
342 + PM_POWUP);
343 +
344 + start = ktime_get_ns();
345 + while (!(powok = !!(PM_READ(pm_reg) & PM_POWOK))) {
346 + cpu_relax();
347 + if (ktime_get_ns() - start >= 3000)
348 + break;
349 + }
350 + }
351 + if (!powok) {
352 + dev_err(dev, "Timeout waiting for %s power OK\n",
353 + pd->base.name);
354 + ret = -ETIMEDOUT;
355 + goto err_disable_powup;
356 + }
357 +
358 + /* Disable electrical isolation */
359 + PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISPOW);
360 +
361 + /* Repair memory */
362 + PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_MEMREP);
363 + start = ktime_get_ns();
364 + while (!(PM_READ(pm_reg) & PM_MRDONE)) {
365 + cpu_relax();
366 + if (ktime_get_ns() - start >= 1000) {
367 + dev_err(dev, "Timeout waiting for %s memory repair\n",
368 + pd->base.name);
369 + ret = -ETIMEDOUT;
370 + goto err_disable_ispow;
371 + }
372 + }
373 +
374 + /* Disable functional isolation */
375 + PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISFUNC);
376 +
377 + return 0;
378 +
379 +err_disable_ispow:
380 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
381 +err_disable_powup:
382 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~(PM_POWUP | PM_INRUSH_MASK));
383 + return ret;
384 +}
385 +
386 +static int bcm2835_asb_power_on(struct bcm2835_power_domain *pd,
387 + u32 pm_reg,
388 + u32 asb_m_reg,
389 + u32 asb_s_reg,
390 + u32 reset_flags)
391 +{
392 + struct bcm2835_power *power = pd->power;
393 + int ret;
394 +
395 + ret = clk_prepare_enable(pd->clk);
396 + if (ret) {
397 + dev_err(power->dev, "Failed to enable clock for %s\n",
398 + pd->base.name);
399 + return ret;
400 + }
401 +
402 + /* Wait 32 clocks for reset to propagate, 1 us will be enough */
403 + udelay(1);
404 +
405 + clk_disable_unprepare(pd->clk);
406 +
407 + /* Deassert the resets. */
408 + PM_WRITE(pm_reg, PM_READ(pm_reg) | reset_flags);
409 +
410 + ret = clk_prepare_enable(pd->clk);
411 + if (ret) {
412 + dev_err(power->dev, "Failed to enable clock for %s\n",
413 + pd->base.name);
414 + goto err_enable_resets;
415 + }
416 +
417 + ret = bcm2835_asb_enable(power, asb_m_reg);
418 + if (ret) {
419 + dev_err(power->dev, "Failed to enable ASB master for %s\n",
420 + pd->base.name);
421 + goto err_disable_clk;
422 + }
423 + ret = bcm2835_asb_enable(power, asb_s_reg);
424 + if (ret) {
425 + dev_err(power->dev, "Failed to enable ASB slave for %s\n",
426 + pd->base.name);
427 + goto err_disable_asb_master;
428 + }
429 +
430 + return 0;
431 +
432 +err_disable_asb_master:
433 + bcm2835_asb_disable(power, asb_m_reg);
434 +err_disable_clk:
435 + clk_disable_unprepare(pd->clk);
436 +err_enable_resets:
437 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
438 + return ret;
439 +}
440 +
441 +static int bcm2835_asb_power_off(struct bcm2835_power_domain *pd,
442 + u32 pm_reg,
443 + u32 asb_m_reg,
444 + u32 asb_s_reg,
445 + u32 reset_flags)
446 +{
447 + struct bcm2835_power *power = pd->power;
448 + int ret;
449 +
450 + ret = bcm2835_asb_disable(power, asb_s_reg);
451 + if (ret) {
452 + dev_warn(power->dev, "Failed to disable ASB slave for %s\n",
453 + pd->base.name);
454 + return ret;
455 + }
456 + ret = bcm2835_asb_disable(power, asb_m_reg);
457 + if (ret) {
458 + dev_warn(power->dev, "Failed to disable ASB master for %s\n",
459 + pd->base.name);
460 + bcm2835_asb_enable(power, asb_s_reg);
461 + return ret;
462 + }
463 +
464 + clk_disable_unprepare(pd->clk);
465 +
466 + /* Assert the resets. */
467 + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
468 +
469 + return 0;
470 +}
471 +
472 +static int bcm2835_power_pd_power_on(struct generic_pm_domain *domain)
473 +{
474 + struct bcm2835_power_domain *pd =
475 + container_of(domain, struct bcm2835_power_domain, base);
476 + struct bcm2835_power *power = pd->power;
477 +
478 + switch (pd->domain) {
479 + case BCM2835_POWER_DOMAIN_GRAFX:
480 + return bcm2835_power_power_on(pd, PM_GRAFX);
481 +
482 + case BCM2835_POWER_DOMAIN_GRAFX_V3D:
483 + return bcm2835_asb_power_on(pd, PM_GRAFX,
484 + ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
485 + PM_V3DRSTN);
486 +
487 + case BCM2835_POWER_DOMAIN_IMAGE:
488 + return bcm2835_power_power_on(pd, PM_IMAGE);
489 +
490 + case BCM2835_POWER_DOMAIN_IMAGE_PERI:
491 + return bcm2835_asb_power_on(pd, PM_IMAGE,
492 + 0, 0,
493 + PM_PERIRSTN);
494 +
495 + case BCM2835_POWER_DOMAIN_IMAGE_ISP:
496 + return bcm2835_asb_power_on(pd, PM_IMAGE,
497 + ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
498 + PM_ISPRSTN);
499 +
500 + case BCM2835_POWER_DOMAIN_IMAGE_H264:
501 + return bcm2835_asb_power_on(pd, PM_IMAGE,
502 + ASB_H264_M_CTRL, ASB_H264_S_CTRL,
503 + PM_H264RSTN);
504 +
505 + case BCM2835_POWER_DOMAIN_USB:
506 + PM_WRITE(PM_USB, PM_USB_CTRLEN);
507 + return 0;
508 +
509 + case BCM2835_POWER_DOMAIN_DSI0:
510 + PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
511 + PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN | PM_DSI0_LDOHPEN);
512 + return 0;
513 +
514 + case BCM2835_POWER_DOMAIN_DSI1:
515 + PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
516 + PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN | PM_DSI1_LDOHPEN);
517 + return 0;
518 +
519 + case BCM2835_POWER_DOMAIN_CCP2TX:
520 + PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
521 + PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN | PM_CCP2TX_LDOEN);
522 + return 0;
523 +
524 + case BCM2835_POWER_DOMAIN_HDMI:
525 + PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_RSTDR);
526 + PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_CTRLEN);
527 + PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_LDOPD);
528 + usleep_range(100, 200);
529 + PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_RSTDR);
530 + return 0;
531 +
532 + default:
533 + dev_err(power->dev, "Invalid domain %d\n", pd->domain);
534 + return -EINVAL;
535 + }
536 +}
537 +
538 +static int bcm2835_power_pd_power_off(struct generic_pm_domain *domain)
539 +{
540 + struct bcm2835_power_domain *pd =
541 + container_of(domain, struct bcm2835_power_domain, base);
542 + struct bcm2835_power *power = pd->power;
543 +
544 + switch (pd->domain) {
545 + case BCM2835_POWER_DOMAIN_GRAFX:
546 + return bcm2835_power_power_off(pd, PM_GRAFX);
547 +
548 + case BCM2835_POWER_DOMAIN_GRAFX_V3D:
549 + return bcm2835_asb_power_off(pd, PM_GRAFX,
550 + ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
551 + PM_V3DRSTN);
552 +
553 + case BCM2835_POWER_DOMAIN_IMAGE:
554 + return bcm2835_power_power_off(pd, PM_IMAGE);
555 +
556 + case BCM2835_POWER_DOMAIN_IMAGE_PERI:
557 + return bcm2835_asb_power_off(pd, PM_IMAGE,
558 + 0, 0,
559 + PM_PERIRSTN);
560 +
561 + case BCM2835_POWER_DOMAIN_IMAGE_ISP:
562 + return bcm2835_asb_power_off(pd, PM_IMAGE,
563 + ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
564 + PM_ISPRSTN);
565 +
566 + case BCM2835_POWER_DOMAIN_IMAGE_H264:
567 + return bcm2835_asb_power_off(pd, PM_IMAGE,
568 + ASB_H264_M_CTRL, ASB_H264_S_CTRL,
569 + PM_H264RSTN);
570 +
571 + case BCM2835_POWER_DOMAIN_USB:
572 + PM_WRITE(PM_USB, 0);
573 + return 0;
574 +
575 + case BCM2835_POWER_DOMAIN_DSI0:
576 + PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
577 + PM_WRITE(PM_DSI0, 0);
578 + return 0;
579 +
580 + case BCM2835_POWER_DOMAIN_DSI1:
581 + PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
582 + PM_WRITE(PM_DSI1, 0);
583 + return 0;
584 +
585 + case BCM2835_POWER_DOMAIN_CCP2TX:
586 + PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
587 + PM_WRITE(PM_CCP2TX, 0);
588 + return 0;
589 +
590 + case BCM2835_POWER_DOMAIN_HDMI:
591 + PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_LDOPD);
592 + PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_CTRLEN);
593 + return 0;
594 +
595 + default:
596 + dev_err(power->dev, "Invalid domain %d\n", pd->domain);
597 + return -EINVAL;
598 + }
599 +}
600 +
601 +static void
602 +bcm2835_init_power_domain(struct bcm2835_power *power,
603 + int pd_xlate_index, const char *name)
604 +{
605 + struct device *dev = power->dev;
606 + struct bcm2835_power_domain *dom = &power->domains[pd_xlate_index];
607 +
608 + dom->clk = devm_clk_get(dev->parent, name);
609 +
610 + dom->base.name = name;
611 + dom->base.power_on = bcm2835_power_pd_power_on;
612 + dom->base.power_off = bcm2835_power_pd_power_off;
613 +
614 + dom->domain = pd_xlate_index;
615 + dom->power = power;
616 +
617 + /* XXX: on/off at boot? */
618 + pm_genpd_init(&dom->base, NULL, true);
619 +
620 + power->pd_xlate.domains[pd_xlate_index] = &dom->base;
621 +}
622 +
623 +/** bcm2835_reset_reset - Resets a block that has a reset line in the
624 + * PM block.
625 + *
626 + * The consumer of the reset controller must have the power domain up
627 + * -- there's no reset ability with the power domain down. To reset
628 + * the sub-block, we just disable its access to memory through the
629 + * ASB, reset, and re-enable.
630 + */
631 +static int bcm2835_reset_reset(struct reset_controller_dev *rcdev,
632 + unsigned long id)
633 +{
634 + struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
635 + reset);
636 + struct bcm2835_power_domain *pd;
637 + int ret;
638 +
639 + switch (id) {
640 + case BCM2835_RESET_V3D:
641 + pd = &power->domains[BCM2835_POWER_DOMAIN_GRAFX_V3D];
642 + break;
643 + case BCM2835_RESET_H264:
644 + pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_H264];
645 + break;
646 + case BCM2835_RESET_ISP:
647 + pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_ISP];
648 + break;
649 + default:
650 + dev_err(power->dev, "Bad reset id %ld\n", id);
651 + return -EINVAL;
652 + }
653 +
654 + ret = bcm2835_power_pd_power_off(&pd->base);
655 + if (ret)
656 + return ret;
657 +
658 + return bcm2835_power_pd_power_on(&pd->base);
659 +}
660 +
661 +static int bcm2835_reset_status(struct reset_controller_dev *rcdev,
662 + unsigned long id)
663 +{
664 + struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
665 + reset);
666 +
667 + switch (id) {
668 + case BCM2835_RESET_V3D:
669 + return !PM_READ(PM_GRAFX & PM_V3DRSTN);
670 + case BCM2835_RESET_H264:
671 + return !PM_READ(PM_IMAGE & PM_H264RSTN);
672 + case BCM2835_RESET_ISP:
673 + return !PM_READ(PM_IMAGE & PM_ISPRSTN);
674 + default:
675 + return -EINVAL;
676 + }
677 +}
678 +
679 +const struct reset_control_ops bcm2835_reset_ops = {
680 + .reset = bcm2835_reset_reset,
681 + .status = bcm2835_reset_status,
682 +};
683 +
684 +static const char *const power_domain_names[] = {
685 + [BCM2835_POWER_DOMAIN_GRAFX] = "grafx",
686 + [BCM2835_POWER_DOMAIN_GRAFX_V3D] = "v3d",
687 +
688 + [BCM2835_POWER_DOMAIN_IMAGE] = "image",
689 + [BCM2835_POWER_DOMAIN_IMAGE_PERI] = "peri_image",
690 + [BCM2835_POWER_DOMAIN_IMAGE_H264] = "h264",
691 + [BCM2835_POWER_DOMAIN_IMAGE_ISP] = "isp",
692 +
693 + [BCM2835_POWER_DOMAIN_USB] = "usb",
694 + [BCM2835_POWER_DOMAIN_DSI0] = "dsi0",
695 + [BCM2835_POWER_DOMAIN_DSI1] = "dsi1",
696 + [BCM2835_POWER_DOMAIN_CAM0] = "cam0",
697 + [BCM2835_POWER_DOMAIN_CAM1] = "cam1",
698 + [BCM2835_POWER_DOMAIN_CCP2TX] = "ccp2tx",
699 + [BCM2835_POWER_DOMAIN_HDMI] = "hdmi",
700 +};
701 +
702 +static int bcm2835_power_probe(struct platform_device *pdev)
703 +{
704 + struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
705 + struct device *dev = &pdev->dev;
706 + struct bcm2835_power *power;
707 + static const struct {
708 + int parent, child;
709 + } domain_deps[] = {
710 + { BCM2835_POWER_DOMAIN_GRAFX, BCM2835_POWER_DOMAIN_GRAFX_V3D },
711 + { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_PERI },
712 + { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_H264 },
713 + { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_ISP },
714 + { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_USB },
715 + { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM0 },
716 + { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM1 },
717 + };
718 + int ret, i;
719 + u32 id;
720 +
721 + power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
722 + if (!power)
723 + return -ENOMEM;
724 + platform_set_drvdata(pdev, power);
725 +
726 + power->dev = dev;
727 + power->base = pm->base;
728 + power->asb = pm->asb;
729 +
730 + id = ASB_READ(ASB_AXI_BRDG_ID);
731 + if (id != 0x62726467 /* "BRDG" */) {
732 + dev_err(dev, "ASB register ID returned 0x%08x\n", id);
733 + return -ENODEV;
734 + }
735 +
736 + power->pd_xlate.domains = devm_kcalloc(dev,
737 + ARRAY_SIZE(power_domain_names),
738 + sizeof(*power->pd_xlate.domains),
739 + GFP_KERNEL);
740 + if (!power->pd_xlate.domains)
741 + return -ENOMEM;
742 +
743 + power->pd_xlate.num_domains = ARRAY_SIZE(power_domain_names);
744 +
745 + for (i = 0; i < ARRAY_SIZE(power_domain_names); i++)
746 + bcm2835_init_power_domain(power, i, power_domain_names[i]);
747 +
748 + for (i = 0; i < ARRAY_SIZE(domain_deps); i++) {
749 + pm_genpd_add_subdomain(&power->domains[domain_deps[i].parent].base,
750 + &power->domains[domain_deps[i].child].base);
751 + }
752 +
753 + power->reset.owner = THIS_MODULE;
754 + power->reset.nr_resets = BCM2835_RESET_COUNT;
755 + power->reset.ops = &bcm2835_reset_ops;
756 + power->reset.of_node = dev->parent->of_node;
757 +
758 + ret = devm_reset_controller_register(dev, &power->reset);
759 + if (ret)
760 + return ret;
761 +
762 + of_genpd_add_provider_onecell(dev->parent->of_node, &power->pd_xlate);
763 +
764 + dev_info(dev, "Broadcom BCM2835 power domains driver");
765 + return 0;
766 +}
767 +
768 +static int bcm2835_power_remove(struct platform_device *pdev)
769 +{
770 + return 0;
771 +}
772 +
773 +static struct platform_driver bcm2835_power_driver = {
774 + .probe = bcm2835_power_probe,
775 + .remove = bcm2835_power_remove,
776 + .driver = {
777 + .name = "bcm2835-power",
778 + },
779 +};
780 +module_platform_driver(bcm2835_power_driver);
781 +
782 +MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
783 +MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM power domains and reset");
784 +MODULE_LICENSE("GPL");
785 --- /dev/null
786 +++ b/include/dt-bindings/soc/bcm2835-pm.h
787 @@ -0,0 +1,28 @@
788 +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
789 +
790 +#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H
791 +#define _DT_BINDINGS_ARM_BCM2835_PM_H
792 +
793 +#define BCM2835_POWER_DOMAIN_GRAFX 0
794 +#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1
795 +#define BCM2835_POWER_DOMAIN_IMAGE 2
796 +#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3
797 +#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4
798 +#define BCM2835_POWER_DOMAIN_IMAGE_H264 5
799 +#define BCM2835_POWER_DOMAIN_USB 6
800 +#define BCM2835_POWER_DOMAIN_DSI0 7
801 +#define BCM2835_POWER_DOMAIN_DSI1 8
802 +#define BCM2835_POWER_DOMAIN_CAM0 9
803 +#define BCM2835_POWER_DOMAIN_CAM1 10
804 +#define BCM2835_POWER_DOMAIN_CCP2TX 11
805 +#define BCM2835_POWER_DOMAIN_HDMI 12
806 +
807 +#define BCM2835_POWER_DOMAIN_COUNT 13
808 +
809 +#define BCM2835_RESET_V3D 0
810 +#define BCM2835_RESET_ISP 1
811 +#define BCM2835_RESET_H264 2
812 +
813 +#define BCM2835_RESET_COUNT 3
814 +
815 +#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */
816 --- a/include/linux/mfd/bcm2835-pm.h
817 +++ b/include/linux/mfd/bcm2835-pm.h
818 @@ -8,6 +8,7 @@
819 struct bcm2835_pm {
820 struct device *dev;
821 void __iomem *base;
822 + void __iomem *asb;
823 };
824
825 #endif /* BCM2835_MFD_PM_H */
lynxis staging tree