git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From d408e9c29dd580cb94e39da2b0eef81061d22061 Mon Sep 17 00:00:00 2001
   2 From: Ran Wang <ran.wang_1@nxp.com>
   3 Date: Thu, 19 Dec 2019 17:02:36 +0800
   4 Subject: [PATCH] LF-387-1 Revert "usb: dwc3: Add cache type configuration
   5  support"
   6
   7 This reverts commit ebceaf435cc96892d22b334b2a6517374c0d6a6e.
   8 Will use next version patch to replace this.
   9
  10 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  11 ---
  12  drivers/usb/dwc3/core.c | 61 +++++--------------------------------------------
  13  drivers/usb/dwc3/core.h | 15 ------------
  14  2 files changed, 6 insertions(+), 70 deletions(-)
  15
  16 --- a/drivers/usb/dwc3/core.c
  17 +++ b/drivers/usb/dwc3/core.c
  18 @@ -913,54 +913,6 @@ static void dwc3_set_power_down_clk_scal
  19         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  20  }
  21
  22 -#ifdef CONFIG_OF
  23 -struct dwc3_cache_type {
  24 -       u8 transfer_type_datard;
  25 -       u8 transfer_type_descrd;
  26 -       u8 transfer_type_datawr;
  27 -       u8 transfer_type_descwr;
  28 -};
  29 -
  30 -static const struct dwc3_cache_type layerscape_dwc3_cache_type = {
  31 -       .transfer_type_datard = 2,
  32 -       .transfer_type_descrd = 2,
  33 -       .transfer_type_datawr = 2,
  34 -       .transfer_type_descwr = 2,
  35 -};
  36 -
  37 -/**
  38 - * dwc3_set_cache_type - Configure cache type registers
  39 - * @dwc: Pointer to our controller context structure
  40 - */
  41 -static void dwc3_set_cache_type(struct dwc3 *dwc)
  42 -{
  43 -       u32 tmp, reg;
  44 -       const struct dwc3_cache_type *cache_type =
  45 -               device_get_match_data(dwc->dev);
  46 -
  47 -       if (cache_type) {
  48 -               reg = dwc3_readl(dwc->regs,  DWC3_GSBUSCFG0);
  49 -               tmp = reg;
  50 -
  51 -               reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
  52 -               reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
  53 -
  54 -               reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
  55 -               reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
  56 -
  57 -               reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
  58 -               reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
  59 -
  60 -               reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
  61 -               reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
  62 -
  63 -               if (tmp != reg)
  64 -                       dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
  65 -       }
  66 -}
  67 -#endif
  68 -
  69 -
  70  /**
  71   * dwc3_core_init - Low-level initialization of DWC3 Core
  72   * @dwc: Pointer to our controller context structure
  73 @@ -1021,10 +973,6 @@ static int dwc3_core_init(struct dwc3 *d
  74
  75         dwc3_set_incr_burst_type(dwc);
  76
  77 -#ifdef CONFIG_OF
  78 -       dwc3_set_cache_type(dwc);
  79 -#endif
  80 -
  81         usb_phy_set_suspend(dwc->usb2_phy, 0);
  82         usb_phy_set_suspend(dwc->usb3_phy, 0);
  83         ret = phy_power_on(dwc->usb2_generic_phy);
  84 @@ -1947,9 +1895,12 @@ static const struct dev_pm_ops dwc3_dev_
  85
  86  #ifdef CONFIG_OF
  87  static const struct of_device_id of_dwc3_match[] = {
  88 -       { .compatible = "fsl,layerscape-dwc3", .data = &layerscape_dwc3_cache_type, },
  89 -       { .compatible = "snps,dwc3" },
  90 -       { .compatible = "synopsys,dwc3" },
  91 +       {
  92 +               .compatible = "snps,dwc3"
  93 +       },
  94 +       {
  95 +               .compatible = "synopsys,dwc3"
  96 +       },
  97         { },
  98  };
  99  MODULE_DEVICE_TABLE(of, of_dwc3_match);
 100 --- a/drivers/usb/dwc3/core.h
 101 +++ b/drivers/usb/dwc3/core.h
 102 @@ -166,21 +166,6 @@
 103  /* Bit fields */
 104
 105  /* Global SoC Bus Configuration INCRx Register 0 */
 106 -#ifdef CONFIG_OF
 107 -#define DWC3_GSBUSCFG0_DATARD_SHIFT    28
 108 -#define DWC3_GSBUSCFG0_DATARD(n)       (((n) & 0xf)            \
 109 -                       << DWC3_GSBUSCFG0_DATARD_SHIFT)
 110 -#define DWC3_GSBUSCFG0_DESCRD_SHIFT    24
 111 -#define DWC3_GSBUSCFG0_DESCRD(n)       (((n) & 0xf)            \
 112 -                       << DWC3_GSBUSCFG0_DESCRD_SHIFT)
 113 -#define DWC3_GSBUSCFG0_DATAWR_SHIFT    20
 114 -#define DWC3_GSBUSCFG0_DATAWR(n)       (((n) & 0xf)            \
 115 -                       << DWC3_GSBUSCFG0_DATAWR_SHIFT)
 116 -#define DWC3_GSBUSCFG0_DESCWR_SHIFT    16
 117 -#define DWC3_GSBUSCFG0_DESCWR(n)       (((n) & 0xf)            \
 118 -                       << DWC3_GSBUSCFG0_DESCWR_SHIFT)
 119 -#endif
 120 -
 121  #define DWC3_GSBUSCFG0_INCR256BRSTENA  (1 << 7) /* INCR256 burst */
 122  #define DWC3_GSBUSCFG0_INCR128BRSTENA  (1 << 6) /* INCR128 burst */
 123  #define DWC3_GSBUSCFG0_INCR64BRSTENA   (1 << 5) /* INCR64 burst */