git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Wed, 27 Oct 2021 00:57:06 +0800
   4 Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Define the Realtek RTL8365MB switch without interrupt support on the device
  10 tree of Asus RT-AC88U.
  11
  12 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  13 Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
  14 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  15 ---
  16  arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++
  17  1 file changed, 77 insertions(+)
  18
  19 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
  20 +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
  21 @@ -93,6 +93,83 @@
  22                         gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
  23                 };
  24         };
  25 +
  26 +       switch {
  27 +               compatible = "realtek,rtl8365mb";
  28 +               /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
  29 +               mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
  30 +               mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
  31 +               reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
  32 +               realtek,disable-leds;
  33 +               dsa,member = <1 0>;
  34 +
  35 +               ports {
  36 +                       #address-cells = <1>;
  37 +                       #size-cells = <0>;
  38 +                       reg = <0>;
  39 +
  40 +                       port@0 {
  41 +                               reg = <0>;
  42 +                               label = "lan5";
  43 +                               phy-handle = <&ethphy0>;
  44 +                       };
  45 +
  46 +                       port@1 {
  47 +                               reg = <1>;
  48 +                               label = "lan6";
  49 +                               phy-handle = <&ethphy1>;
  50 +                       };
  51 +
  52 +                       port@2 {
  53 +                               reg = <2>;
  54 +                               label = "lan7";
  55 +                               phy-handle = <&ethphy2>;
  56 +                       };
  57 +
  58 +                       port@3 {
  59 +                               reg = <3>;
  60 +                               label = "lan8";
  61 +                               phy-handle = <&ethphy3>;
  62 +                       };
  63 +
  64 +                       port@6 {
  65 +                               reg = <6>;
  66 +                               label = "cpu";
  67 +                               ethernet = <&sw0_p5>;
  68 +                               phy-mode = "rgmii";
  69 +                               tx-internal-delay-ps = <2000>;
  70 +                               rx-internal-delay-ps = <2000>;
  71 +
  72 +                               fixed-link {
  73 +                                       speed = <1000>;
  74 +                                       full-duplex;
  75 +                                       pause;
  76 +                               };
  77 +                       };
  78 +               };
  79 +
  80 +               mdio {
  81 +                       compatible = "realtek,smi-mdio";
  82 +                       #address-cells = <1>;
  83 +                       #size-cells = <0>;
  84 +
  85 +                       ethphy0: ethernet-phy@0 {
  86 +                               reg = <0>;
  87 +                       };
  88 +
  89 +                       ethphy1: ethernet-phy@1 {
  90 +                               reg = <1>;
  91 +                       };
  92 +
  93 +                       ethphy2: ethernet-phy@2 {
  94 +                               reg = <2>;
  95 +                       };
  96 +
  97 +                       ethphy3: ethernet-phy@3 {
  98 +                               reg = <3>;
  99 +                       };
 100 +               };
 101 +       };
 102  };
 103
 104  &srab {