git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 85a9cab9b9bb471eae016cdbfabd928585c23cce Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Mon, 4 Jul 2022 13:33:18 +0200
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC node
   5
   6 The ARM timer is usually considered not part of SoC node, just like
   7 other ARM designed blocks (PMU, PSCI).  This fixes dtbs_check warning:
   8
   9 arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
  10         From schema: dtschema/schemas/simple-bus.yaml
  11
  12 Signed-off-by: Robert Marko <robimarko@gmail.com>
  13 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  14 [bjorn: Moved node after "soc" for alphabetical ordering]
  15 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  16 Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
  17 ---
  18  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
  19  1 file changed, 8 insertions(+), 8 deletions(-)
  20
  21 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  22 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  23 @@ -654,14 +654,6 @@
  24                         };
  25                 };
  26
  27 -               timer {
  28 -                       compatible = "arm,armv8-timer";
  29 -                       interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  30 -                                    <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  31 -                                    <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  32 -                                    <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  33 -               };
  34 -
  35                 watchdog: watchdog@b017000 {
  36                         compatible = "qcom,kpss-wdt";
  37                         reg = <0xb017000 0x1000>;
  38 @@ -853,4 +845,12 @@
  39                         status = "disabled";
  40                 };
  41         };
  42 +
  43 +       timer {
  44 +               compatible = "arm,armv8-timer";
  45 +               interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  46 +                            <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  47 +                            <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  48 +                            <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  49 +       };
  50  };