projects / openwrt / staging / 981213.git / blob
? search:


597dcea4c06955a2c23503d96fa147bf020c8711
[openwrt/staging/981213.git] /
1 From c89414adf2ec7cd9e7080c419aa5847f1db1009c Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Mon, 29 Jan 2024 15:15:23 +0100
4 Subject: [PATCH 5/5] net: phy: qcom: detach qca808x PHY driver from at803x
5
6 Almost all the QCA8081 PHY driver OPs are specific and only some of them
7 use the generic at803x.
8
9 To make the at803x code slimmer, move all the specific qca808x regs and
10 functions to a dedicated PHY driver.
11
12 Probe function and priv struct is reworked to allocate and use only the
13 qca808x specific data. Unused data from at803x PHY driver are dropped
14 from at803x priv struct.
15
16 Also a new Kconfig is introduced QCA808X_PHY, to compile the newly
17 introduced PHY driver for QCA8081 PHY.
18
19 As the Kconfig name starts with Qualcomm the same order is kept.
20
21 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
22 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
23 Link: https://lore.kernel.org/r/20240129141600.2592-6-ansuelsmth@gmail.com
24 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
25 ---
26 drivers/net/phy/qcom/Kconfig | 6 +
27 drivers/net/phy/qcom/Makefile | 1 +
28 drivers/net/phy/qcom/at803x.c | 897 +------------------------------
29 drivers/net/phy/qcom/qca808x.c | 934 +++++++++++++++++++++++++++++++++
30 4 files changed, 942 insertions(+), 896 deletions(-)
31 create mode 100644 drivers/net/phy/qcom/qca808x.c
32
33 --- a/drivers/net/phy/qcom/Kconfig
34 +++ b/drivers/net/phy/qcom/Kconfig
35 @@ -14,3 +14,9 @@ config QCA83XX_PHY
36 select QCOM_NET_PHYLIB
37 help
38 Currently supports the internal QCA8337(Internal qca8k PHY) model
39 +
40 +config QCA808X_PHY
41 + tristate "Qualcomm QCA808x PHYs"
42 + select QCOM_NET_PHYLIB
43 + help
44 + Currently supports the QCA8081 model
45 --- a/drivers/net/phy/qcom/Makefile
46 +++ b/drivers/net/phy/qcom/Makefile
47 @@ -2,3 +2,4 @@
48 obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o
49 obj-$(CONFIG_AT803X_PHY) += at803x.o
50 obj-$(CONFIG_QCA83XX_PHY) += qca83xx.o
51 +obj-$(CONFIG_QCA808X_PHY) += qca808x.o
52 --- a/drivers/net/phy/qcom/at803x.c
53 +++ b/drivers/net/phy/qcom/at803x.c
54 @@ -96,8 +96,6 @@
55 #define ATH8035_PHY_ID 0x004dd072
56 #define AT8030_PHY_ID_MASK 0xffffffef
57
58 -#define QCA8081_PHY_ID 0x004dd101
59 -
60 #define QCA9561_PHY_ID 0x004dd042
61
62 #define AT803X_PAGE_FIBER 0
63 @@ -110,201 +108,7 @@
64 /* disable hibernation mode */
65 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
66
67 -/* ADC threshold */
68 -#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
69 -#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
70 -#define QCA808X_ADC_THRESHOLD_80MV 0
71 -#define QCA808X_ADC_THRESHOLD_100MV 0xf0
72 -#define QCA808X_ADC_THRESHOLD_200MV 0x0f
73 -#define QCA808X_ADC_THRESHOLD_300MV 0xff
74 -
75 -/* CLD control */
76 -#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
77 -#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
78 -#define QCA808X_8023AZ_AFE_EN 0x90
79 -
80 -/* AZ control */
81 -#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
82 -#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
83 -
84 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
85 -#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
86 -
87 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
88 -#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
89 -
90 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
91 -#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
92 -
93 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
94 -#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
95 -
96 -#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
97 -#define QCA808X_TOP_OPTION1_DATA 0x0
98 -
99 -#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
100 -#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
101 -#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
102 -#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
103 -#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
104 -#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
105 -#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
106 -#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
107 -#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
108 -#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
109 -#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
110 -#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
111 -
112 -/* master/slave seed config */
113 -#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
114 -#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
115 -#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
116 -#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
117 -
118 -/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
119 - * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
120 - */
121 -#define QCA808X_DBG_AN_TEST 0xb
122 -#define QCA808X_HIBERNATION_EN BIT(15)
123 -
124 -#define QCA808X_CDT_ENABLE_TEST BIT(15)
125 -#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
126 -#define QCA808X_CDT_STATUS BIT(11)
127 -#define QCA808X_CDT_LENGTH_UNIT BIT(10)
128 -
129 -#define QCA808X_MMD3_CDT_STATUS 0x8064
130 -#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
131 -#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
132 -#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
133 -#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
134 -#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8)
135 -#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0)
136 -
137 -#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
138 -#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
139 -#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
140 -#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
141 -
142 -#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0)
143 -#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
144 -#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
145 -#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
146 -#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
147 -
148 -#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2)
149 -#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
150 -#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
151 -#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
152 -
153 -/* NORMAL are MDI with type set to 0 */
154 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1
155 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
156 - QCA808X_CDT_STATUS_STAT_MDI1)
157 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
158 - QCA808X_CDT_STATUS_STAT_MDI1)
159 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2
160 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
161 - QCA808X_CDT_STATUS_STAT_MDI2)
162 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
163 - QCA808X_CDT_STATUS_STAT_MDI2)
164 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3
165 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
166 - QCA808X_CDT_STATUS_STAT_MDI3)
167 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
168 - QCA808X_CDT_STATUS_STAT_MDI3)
169 -
170 -/* Added for reference of existence but should be handled by wait_for_completion already */
171 -#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3))
172 -
173 -#define QCA808X_MMD7_LED_GLOBAL 0x8073
174 -#define QCA808X_LED_BLINK_1 GENMASK(11, 6)
175 -#define QCA808X_LED_BLINK_2 GENMASK(5, 0)
176 -/* Values are the same for both BLINK_1 and BLINK_2 */
177 -#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3)
178 -#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
179 -#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
180 -#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
181 -#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
182 -#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
183 -#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
184 -#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
185 -#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
186 -#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0)
187 -#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
188 -#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
189 -#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
190 -#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
191 -#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
192 -#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
193 -#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
194 -#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
195 -
196 -#define QCA808X_MMD7_LED2_CTRL 0x8074
197 -#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075
198 -#define QCA808X_MMD7_LED1_CTRL 0x8076
199 -#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077
200 -#define QCA808X_MMD7_LED0_CTRL 0x8078
201 -#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2))
202 -
203 -/* LED hw control pattern is the same for every LED */
204 -#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0)
205 -#define QCA808X_LED_SPEED2500_ON BIT(15)
206 -#define QCA808X_LED_SPEED2500_BLINK BIT(14)
207 -/* Follow blink trigger even if duplex or speed condition doesn't match */
208 -#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13)
209 -#define QCA808X_LED_FULL_DUPLEX_ON BIT(12)
210 -#define QCA808X_LED_HALF_DUPLEX_ON BIT(11)
211 -#define QCA808X_LED_TX_BLINK BIT(10)
212 -#define QCA808X_LED_RX_BLINK BIT(9)
213 -#define QCA808X_LED_TX_ON_10MS BIT(8)
214 -#define QCA808X_LED_RX_ON_10MS BIT(7)
215 -#define QCA808X_LED_SPEED1000_ON BIT(6)
216 -#define QCA808X_LED_SPEED100_ON BIT(5)
217 -#define QCA808X_LED_SPEED10_ON BIT(4)
218 -#define QCA808X_LED_COLLISION_BLINK BIT(3)
219 -#define QCA808X_LED_SPEED1000_BLINK BIT(2)
220 -#define QCA808X_LED_SPEED100_BLINK BIT(1)
221 -#define QCA808X_LED_SPEED10_BLINK BIT(0)
222 -
223 -#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079
224 -#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2))
225 -
226 -/* LED force ctrl is the same for every LED
227 - * No documentation exist for this, not even internal one
228 - * with NDA as QCOM gives only info about configuring
229 - * hw control pattern rules and doesn't indicate any way
230 - * to force the LED to specific mode.
231 - * These define comes from reverse and testing and maybe
232 - * lack of some info or some info are not entirely correct.
233 - * For the basic LED control and hw control these finding
234 - * are enough to support LED control in all the required APIs.
235 - *
236 - * On doing some comparison with implementation with qca807x,
237 - * it was found that it's 1:1 equal to it and confirms all the
238 - * reverse done. It was also found further specification with the
239 - * force mode and the blink modes.
240 - */
241 -#define QCA808X_LED_FORCE_EN BIT(15)
242 -#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13)
243 -#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
244 -#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
245 -#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
246 -#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
247 -
248 -#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a
249 -/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
250 - * LED to active high. It's not clear what BIT 3 and BIT 4 does.
251 - */
252 -#define QCA808X_LED_ACTIVE_HIGH BIT(6)
253 -
254 -/* QCA808X 1G chip type */
255 -#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
256 -#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
257 -
258 -#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
259 -#define QCA8081_PHY_FIFO_RSTN BIT(11)
260 -
261 -MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
262 +MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
263 MODULE_AUTHOR("Matus Ujhelyi");
264 MODULE_LICENSE("GPL");
265
266 @@ -318,7 +122,6 @@ struct at803x_priv {
267 bool is_1000basex;
268 struct regulator_dev *vddio_rdev;
269 struct regulator_dev *vddh_rdev;
270 - int led_polarity_mode;
271 };
272
273 struct at803x_context {
274 @@ -519,9 +322,6 @@ static int at803x_probe(struct phy_devic
275 if (!priv)
276 return -ENOMEM;
277
278 - /* Init LED polarity mode to -1 */
279 - priv->led_polarity_mode = -1;
280 -
281 phydev->priv = priv;
282
283 ret = at803x_parse_dt(phydev);
284 @@ -1216,672 +1016,6 @@ static int at8035_probe(struct phy_devic
285 return at8035_parse_dt(phydev);
286 }
287
288 -static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
289 -{
290 - int ret;
291 -
292 - /* Enable fast retrain */
293 - ret = genphy_c45_fast_retrain(phydev, true);
294 - if (ret)
295 - return ret;
296 -
297 - phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
298 - QCA808X_TOP_OPTION1_DATA);
299 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
300 - QCA808X_MSE_THRESHOLD_20DB_VALUE);
301 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
302 - QCA808X_MSE_THRESHOLD_17DB_VALUE);
303 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
304 - QCA808X_MSE_THRESHOLD_27DB_VALUE);
305 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
306 - QCA808X_MSE_THRESHOLD_28DB_VALUE);
307 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
308 - QCA808X_MMD3_DEBUG_1_VALUE);
309 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
310 - QCA808X_MMD3_DEBUG_4_VALUE);
311 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
312 - QCA808X_MMD3_DEBUG_5_VALUE);
313 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
314 - QCA808X_MMD3_DEBUG_3_VALUE);
315 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
316 - QCA808X_MMD3_DEBUG_6_VALUE);
317 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
318 - QCA808X_MMD3_DEBUG_2_VALUE);
319 -
320 - return 0;
321 -}
322 -
323 -static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
324 -{
325 - u16 seed_value;
326 -
327 - if (!enable)
328 - return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
329 - QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
330 -
331 - seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
332 - return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
333 - QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
334 - FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
335 - QCA808X_MASTER_SLAVE_SEED_ENABLE);
336 -}
337 -
338 -static bool qca808x_is_prefer_master(struct phy_device *phydev)
339 -{
340 - return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
341 - (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
342 -}
343 -
344 -static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
345 -{
346 - return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
347 -}
348 -
349 -static int qca808x_config_init(struct phy_device *phydev)
350 -{
351 - int ret;
352 -
353 - /* Active adc&vga on 802.3az for the link 1000M and 100M */
354 - ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
355 - QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
356 - if (ret)
357 - return ret;
358 -
359 - /* Adjust the threshold on 802.3az for the link 1000M */
360 - ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
361 - QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
362 - QCA808X_MMD3_AZ_TRAINING_VAL);
363 - if (ret)
364 - return ret;
365 -
366 - if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
367 - /* Config the fast retrain for the link 2500M */
368 - ret = qca808x_phy_fast_retrain_config(phydev);
369 - if (ret)
370 - return ret;
371 -
372 - ret = genphy_read_master_slave(phydev);
373 - if (ret < 0)
374 - return ret;
375 -
376 - if (!qca808x_is_prefer_master(phydev)) {
377 - /* Enable seed and configure lower ramdom seed to make phy
378 - * linked as slave mode.
379 - */
380 - ret = qca808x_phy_ms_seed_enable(phydev, true);
381 - if (ret)
382 - return ret;
383 - }
384 - }
385 -
386 - /* Configure adc threshold as 100mv for the link 10M */
387 - return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
388 - QCA808X_ADC_THRESHOLD_MASK,
389 - QCA808X_ADC_THRESHOLD_100MV);
390 -}
391 -
392 -static int qca808x_read_status(struct phy_device *phydev)
393 -{
394 - struct at803x_ss_mask ss_mask = { 0 };
395 - int ret;
396 -
397 - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
398 - if (ret < 0)
399 - return ret;
400 -
401 - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
402 - ret & MDIO_AN_10GBT_STAT_LP2_5G);
403 -
404 - ret = genphy_read_status(phydev);
405 - if (ret)
406 - return ret;
407 -
408 - /* qca8081 takes the different bits for speed value from at803x */
409 - ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
410 - ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
411 - ret = at803x_read_specific_status(phydev, ss_mask);
412 - if (ret < 0)
413 - return ret;
414 -
415 - if (phydev->link) {
416 - if (phydev->speed == SPEED_2500)
417 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
418 - else
419 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
420 - } else {
421 - /* generate seed as a lower random value to make PHY linked as SLAVE easily,
422 - * except for master/slave configuration fault detected or the master mode
423 - * preferred.
424 - *
425 - * the reason for not putting this code into the function link_change_notify is
426 - * the corner case where the link partner is also the qca8081 PHY and the seed
427 - * value is configured as the same value, the link can't be up and no link change
428 - * occurs.
429 - */
430 - if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
431 - if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
432 - qca808x_is_prefer_master(phydev)) {
433 - qca808x_phy_ms_seed_enable(phydev, false);
434 - } else {
435 - qca808x_phy_ms_seed_enable(phydev, true);
436 - }
437 - }
438 - }
439 -
440 - return 0;
441 -}
442 -
443 -static int qca808x_soft_reset(struct phy_device *phydev)
444 -{
445 - int ret;
446 -
447 - ret = genphy_soft_reset(phydev);
448 - if (ret < 0)
449 - return ret;
450 -
451 - if (qca808x_has_fast_retrain_or_slave_seed(phydev))
452 - ret = qca808x_phy_ms_seed_enable(phydev, true);
453 -
454 - return ret;
455 -}
456 -
457 -static bool qca808x_cdt_fault_length_valid(int cdt_code)
458 -{
459 - switch (cdt_code) {
460 - case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
461 - case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
462 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
463 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
464 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
465 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
466 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
467 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
468 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
469 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
470 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
471 - return true;
472 - default:
473 - return false;
474 - }
475 -}
476 -
477 -static int qca808x_cable_test_result_trans(int cdt_code)
478 -{
479 - switch (cdt_code) {
480 - case QCA808X_CDT_STATUS_STAT_NORMAL:
481 - return ETHTOOL_A_CABLE_RESULT_CODE_OK;
482 - case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
483 - return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
484 - case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
485 - return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
486 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
487 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
488 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
489 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
490 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
491 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
492 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
493 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
494 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
495 - return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
496 - case QCA808X_CDT_STATUS_STAT_FAIL:
497 - default:
498 - return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
499 - }
500 -}
501 -
502 -static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
503 - int result)
504 -{
505 - int val;
506 - u32 cdt_length_reg = 0;
507 -
508 - switch (pair) {
509 - case ETHTOOL_A_CABLE_PAIR_A:
510 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
511 - break;
512 - case ETHTOOL_A_CABLE_PAIR_B:
513 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
514 - break;
515 - case ETHTOOL_A_CABLE_PAIR_C:
516 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
517 - break;
518 - case ETHTOOL_A_CABLE_PAIR_D:
519 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
520 - break;
521 - default:
522 - return -EINVAL;
523 - }
524 -
525 - val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
526 - if (val < 0)
527 - return val;
528 -
529 - if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
530 - val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
531 - else
532 - val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
533 -
534 - return at803x_cdt_fault_length(val);
535 -}
536 -
537 -static int qca808x_cable_test_start(struct phy_device *phydev)
538 -{
539 - int ret;
540 -
541 - /* perform CDT with the following configs:
542 - * 1. disable hibernation.
543 - * 2. force PHY working in MDI mode.
544 - * 3. for PHY working in 1000BaseT.
545 - * 4. configure the threshold.
546 - */
547 -
548 - ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
549 - if (ret < 0)
550 - return ret;
551 -
552 - ret = at803x_config_mdix(phydev, ETH_TP_MDI);
553 - if (ret < 0)
554 - return ret;
555 -
556 - /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
557 - phydev->duplex = DUPLEX_FULL;
558 - phydev->speed = SPEED_1000;
559 - ret = genphy_c45_pma_setup_forced(phydev);
560 - if (ret < 0)
561 - return ret;
562 -
563 - ret = genphy_setup_forced(phydev);
564 - if (ret < 0)
565 - return ret;
566 -
567 - /* configure the thresholds for open, short, pair ok test */
568 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
569 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
570 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
571 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
572 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
573 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
574 -
575 - return 0;
576 -}
577 -
578 -static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
579 - u16 status)
580 -{
581 - int length, result;
582 - u16 pair_code;
583 -
584 - switch (pair) {
585 - case ETHTOOL_A_CABLE_PAIR_A:
586 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
587 - break;
588 - case ETHTOOL_A_CABLE_PAIR_B:
589 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
590 - break;
591 - case ETHTOOL_A_CABLE_PAIR_C:
592 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
593 - break;
594 - case ETHTOOL_A_CABLE_PAIR_D:
595 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
596 - break;
597 - default:
598 - return -EINVAL;
599 - }
600 -
601 - result = qca808x_cable_test_result_trans(pair_code);
602 - ethnl_cable_test_result(phydev, pair, result);
603 -
604 - if (qca808x_cdt_fault_length_valid(pair_code)) {
605 - length = qca808x_cdt_fault_length(phydev, pair, result);
606 - ethnl_cable_test_fault_length(phydev, pair, length);
607 - }
608 -
609 - return 0;
610 -}
611 -
612 -static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
613 -{
614 - int ret, val;
615 -
616 - *finished = false;
617 -
618 - val = QCA808X_CDT_ENABLE_TEST |
619 - QCA808X_CDT_LENGTH_UNIT;
620 - ret = at803x_cdt_start(phydev, val);
621 - if (ret)
622 - return ret;
623 -
624 - ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
625 - if (ret)
626 - return ret;
627 -
628 - val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
629 - if (val < 0)
630 - return val;
631 -
632 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
633 - if (ret)
634 - return ret;
635 -
636 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
637 - if (ret)
638 - return ret;
639 -
640 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
641 - if (ret)
642 - return ret;
643 -
644 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
645 - if (ret)
646 - return ret;
647 -
648 - *finished = true;
649 -
650 - return 0;
651 -}
652 -
653 -static int qca808x_get_features(struct phy_device *phydev)
654 -{
655 - int ret;
656 -
657 - ret = genphy_c45_pma_read_abilities(phydev);
658 - if (ret)
659 - return ret;
660 -
661 - /* The autoneg ability is not existed in bit3 of MMD7.1,
662 - * but it is supported by qca808x PHY, so we add it here
663 - * manually.
664 - */
665 - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
666 -
667 - /* As for the qca8081 1G version chip, the 2500baseT ability is also
668 - * existed in the bit0 of MMD1.21, we need to remove it manually if
669 - * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
670 - */
671 - ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
672 - if (ret < 0)
673 - return ret;
674 -
675 - if (QCA808X_PHY_CHIP_TYPE_1G & ret)
676 - linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
677 -
678 - return 0;
679 -}
680 -
681 -static int qca808x_config_aneg(struct phy_device *phydev)
682 -{
683 - int phy_ctrl = 0;
684 - int ret;
685 -
686 - ret = at803x_prepare_config_aneg(phydev);
687 - if (ret)
688 - return ret;
689 -
690 - /* The reg MII_BMCR also needs to be configured for force mode, the
691 - * genphy_config_aneg is also needed.
692 - */
693 - if (phydev->autoneg == AUTONEG_DISABLE)
694 - genphy_c45_pma_setup_forced(phydev);
695 -
696 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
697 - phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
698 -
699 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
700 - MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
701 - if (ret < 0)
702 - return ret;
703 -
704 - return __genphy_config_aneg(phydev, ret);
705 -}
706 -
707 -static void qca808x_link_change_notify(struct phy_device *phydev)
708 -{
709 - /* Assert interface sgmii fifo on link down, deassert it on link up,
710 - * the interface device address is always phy address added by 1.
711 - */
712 - mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
713 - MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
714 - QCA8081_PHY_FIFO_RSTN,
715 - phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
716 -}
717 -
718 -static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
719 - u16 *offload_trigger)
720 -{
721 - /* Parsing specific to netdev trigger */
722 - if (test_bit(TRIGGER_NETDEV_TX, &rules))
723 - *offload_trigger |= QCA808X_LED_TX_BLINK;
724 - if (test_bit(TRIGGER_NETDEV_RX, &rules))
725 - *offload_trigger |= QCA808X_LED_RX_BLINK;
726 - if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
727 - *offload_trigger |= QCA808X_LED_SPEED10_ON;
728 - if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
729 - *offload_trigger |= QCA808X_LED_SPEED100_ON;
730 - if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
731 - *offload_trigger |= QCA808X_LED_SPEED1000_ON;
732 - if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
733 - *offload_trigger |= QCA808X_LED_SPEED2500_ON;
734 - if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
735 - *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
736 - if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
737 - *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
738 -
739 - if (rules && !*offload_trigger)
740 - return -EOPNOTSUPP;
741 -
742 - /* Enable BLINK_CHECK_BYPASS by default to make the LED
743 - * blink even with duplex or speed mode not enabled.
744 - */
745 - *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
746 -
747 - return 0;
748 -}
749 -
750 -static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
751 -{
752 - u16 reg;
753 -
754 - if (index > 2)
755 - return -EINVAL;
756 -
757 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
758 -
759 - return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
760 - QCA808X_LED_FORCE_EN);
761 -}
762 -
763 -static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
764 - unsigned long rules)
765 -{
766 - u16 offload_trigger = 0;
767 -
768 - if (index > 2)
769 - return -EINVAL;
770 -
771 - return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
772 -}
773 -
774 -static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
775 - unsigned long rules)
776 -{
777 - u16 reg, offload_trigger = 0;
778 - int ret;
779 -
780 - if (index > 2)
781 - return -EINVAL;
782 -
783 - reg = QCA808X_MMD7_LED_CTRL(index);
784 -
785 - ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
786 - if (ret)
787 - return ret;
788 -
789 - ret = qca808x_led_hw_control_enable(phydev, index);
790 - if (ret)
791 - return ret;
792 -
793 - return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
794 - QCA808X_LED_PATTERN_MASK,
795 - offload_trigger);
796 -}
797 -
798 -static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
799 -{
800 - u16 reg;
801 - int val;
802 -
803 - if (index > 2)
804 - return false;
805 -
806 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
807 -
808 - val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
809 -
810 - return !(val & QCA808X_LED_FORCE_EN);
811 -}
812 -
813 -static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
814 - unsigned long *rules)
815 -{
816 - u16 reg;
817 - int val;
818 -
819 - if (index > 2)
820 - return -EINVAL;
821 -
822 - /* Check if we have hw control enabled */
823 - if (qca808x_led_hw_control_status(phydev, index))
824 - return -EINVAL;
825 -
826 - reg = QCA808X_MMD7_LED_CTRL(index);
827 -
828 - val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
829 - if (val & QCA808X_LED_TX_BLINK)
830 - set_bit(TRIGGER_NETDEV_TX, rules);
831 - if (val & QCA808X_LED_RX_BLINK)
832 - set_bit(TRIGGER_NETDEV_RX, rules);
833 - if (val & QCA808X_LED_SPEED10_ON)
834 - set_bit(TRIGGER_NETDEV_LINK_10, rules);
835 - if (val & QCA808X_LED_SPEED100_ON)
836 - set_bit(TRIGGER_NETDEV_LINK_100, rules);
837 - if (val & QCA808X_LED_SPEED1000_ON)
838 - set_bit(TRIGGER_NETDEV_LINK_1000, rules);
839 - if (val & QCA808X_LED_SPEED2500_ON)
840 - set_bit(TRIGGER_NETDEV_LINK_2500, rules);
841 - if (val & QCA808X_LED_HALF_DUPLEX_ON)
842 - set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
843 - if (val & QCA808X_LED_FULL_DUPLEX_ON)
844 - set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
845 -
846 - return 0;
847 -}
848 -
849 -static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
850 -{
851 - u16 reg;
852 -
853 - if (index > 2)
854 - return -EINVAL;
855 -
856 - reg = QCA808X_MMD7_LED_CTRL(index);
857 -
858 - return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
859 - QCA808X_LED_PATTERN_MASK);
860 -}
861 -
862 -static int qca808x_led_brightness_set(struct phy_device *phydev,
863 - u8 index, enum led_brightness value)
864 -{
865 - u16 reg;
866 - int ret;
867 -
868 - if (index > 2)
869 - return -EINVAL;
870 -
871 - if (!value) {
872 - ret = qca808x_led_hw_control_reset(phydev, index);
873 - if (ret)
874 - return ret;
875 - }
876 -
877 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
878 -
879 - return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
880 - QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
881 - QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
882 - QCA808X_LED_FORCE_OFF);
883 -}
884 -
885 -static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
886 - unsigned long *delay_on,
887 - unsigned long *delay_off)
888 -{
889 - int ret;
890 - u16 reg;
891 -
892 - if (index > 2)
893 - return -EINVAL;
894 -
895 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
896 -
897 - /* Set blink to 50% off, 50% on at 4Hz by default */
898 - ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
899 - QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
900 - QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
901 - if (ret)
902 - return ret;
903 -
904 - /* We use BLINK_1 for normal blinking */
905 - ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
906 - QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
907 - QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
908 - if (ret)
909 - return ret;
910 -
911 - /* We set blink to 4Hz, aka 250ms */
912 - *delay_on = 250 / 2;
913 - *delay_off = 250 / 2;
914 -
915 - return 0;
916 -}
917 -
918 -static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
919 - unsigned long modes)
920 -{
921 - struct at803x_priv *priv = phydev->priv;
922 - bool active_low = false;
923 - u32 mode;
924 -
925 - for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
926 - switch (mode) {
927 - case PHY_LED_ACTIVE_LOW:
928 - active_low = true;
929 - break;
930 - default:
931 - return -EINVAL;
932 - }
933 - }
934 -
935 - /* PHY polarity is global and can't be set per LED.
936 - * To detect this, check if last requested polarity mode
937 - * match the new one.
938 - */
939 - if (priv->led_polarity_mode >= 0 &&
940 - priv->led_polarity_mode != active_low) {
941 - phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
942 - return -EINVAL;
943 - }
944 -
945 - /* Save the last PHY polarity mode */
946 - priv->led_polarity_mode = active_low;
947 -
948 - return phy_modify_mmd(phydev, MDIO_MMD_AN,
949 - QCA808X_MMD7_LED_POLARITY_CTRL,
950 - QCA808X_LED_ACTIVE_HIGH,
951 - active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
952 -}
953 -
954 static struct phy_driver at803x_driver[] = {
955 {
956 /* Qualcomm Atheros AR8035 */
957 @@ -1989,34 +1123,6 @@ static struct phy_driver at803x_driver[]
958 .read_status = at803x_read_status,
959 .soft_reset = genphy_soft_reset,
960 .config_aneg = at803x_config_aneg,
961 -}, {
962 - /* Qualcomm QCA8081 */
963 - PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
964 - .name = "Qualcomm QCA8081",
965 - .flags = PHY_POLL_CABLE_TEST,
966 - .probe = at803x_probe,
967 - .config_intr = at803x_config_intr,
968 - .handle_interrupt = at803x_handle_interrupt,
969 - .get_tunable = at803x_get_tunable,
970 - .set_tunable = at803x_set_tunable,
971 - .set_wol = at803x_set_wol,
972 - .get_wol = at803x_get_wol,
973 - .get_features = qca808x_get_features,
974 - .config_aneg = qca808x_config_aneg,
975 - .suspend = genphy_suspend,
976 - .resume = genphy_resume,
977 - .read_status = qca808x_read_status,
978 - .config_init = qca808x_config_init,
979 - .soft_reset = qca808x_soft_reset,
980 - .cable_test_start = qca808x_cable_test_start,
981 - .cable_test_get_status = qca808x_cable_test_get_status,
982 - .link_change_notify = qca808x_link_change_notify,
983 - .led_brightness_set = qca808x_led_brightness_set,
984 - .led_blink_set = qca808x_led_blink_set,
985 - .led_hw_is_supported = qca808x_led_hw_is_supported,
986 - .led_hw_control_set = qca808x_led_hw_control_set,
987 - .led_hw_control_get = qca808x_led_hw_control_get,
988 - .led_polarity_set = qca808x_led_polarity_set,
989 }, };
990
991 module_phy_driver(at803x_driver);
992 @@ -2028,7 +1134,6 @@ static struct mdio_device_id __maybe_unu
993 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
994 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
995 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
996 - { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
997 { }
998 };
999
1000 --- /dev/null
1001 +++ b/drivers/net/phy/qcom/qca808x.c
1002 @@ -0,0 +1,934 @@
1003 +// SPDX-License-Identifier: GPL-2.0+
1004 +
1005 +#include <linux/phy.h>
1006 +#include <linux/module.h>
1007 +#include <linux/ethtool_netlink.h>
1008 +
1009 +#include "qcom.h"
1010 +
1011 +/* ADC threshold */
1012 +#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
1013 +#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
1014 +#define QCA808X_ADC_THRESHOLD_80MV 0
1015 +#define QCA808X_ADC_THRESHOLD_100MV 0xf0
1016 +#define QCA808X_ADC_THRESHOLD_200MV 0x0f
1017 +#define QCA808X_ADC_THRESHOLD_300MV 0xff
1018 +
1019 +/* CLD control */
1020 +#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
1021 +#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
1022 +#define QCA808X_8023AZ_AFE_EN 0x90
1023 +
1024 +/* AZ control */
1025 +#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
1026 +#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
1027 +
1028 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
1029 +#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
1030 +
1031 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
1032 +#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
1033 +
1034 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
1035 +#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
1036 +
1037 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
1038 +#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
1039 +
1040 +#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
1041 +#define QCA808X_TOP_OPTION1_DATA 0x0
1042 +
1043 +#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
1044 +#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
1045 +#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
1046 +#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
1047 +#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
1048 +#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
1049 +#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
1050 +#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
1051 +#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
1052 +#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
1053 +#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
1054 +#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
1055 +
1056 +/* master/slave seed config */
1057 +#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
1058 +#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
1059 +#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
1060 +#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
1061 +
1062 +/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
1063 + * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
1064 + */
1065 +#define QCA808X_DBG_AN_TEST 0xb
1066 +#define QCA808X_HIBERNATION_EN BIT(15)
1067 +
1068 +#define QCA808X_CDT_ENABLE_TEST BIT(15)
1069 +#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
1070 +#define QCA808X_CDT_STATUS BIT(11)
1071 +#define QCA808X_CDT_LENGTH_UNIT BIT(10)
1072 +
1073 +#define QCA808X_MMD3_CDT_STATUS 0x8064
1074 +#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
1075 +#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
1076 +#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
1077 +#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
1078 +#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8)
1079 +#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0)
1080 +
1081 +#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
1082 +#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
1083 +#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
1084 +#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
1085 +
1086 +#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0)
1087 +#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
1088 +#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
1089 +#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
1090 +#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
1091 +
1092 +#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2)
1093 +#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
1094 +#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
1095 +#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
1096 +
1097 +/* NORMAL are MDI with type set to 0 */
1098 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1
1099 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
1100 + QCA808X_CDT_STATUS_STAT_MDI1)
1101 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
1102 + QCA808X_CDT_STATUS_STAT_MDI1)
1103 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2
1104 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
1105 + QCA808X_CDT_STATUS_STAT_MDI2)
1106 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
1107 + QCA808X_CDT_STATUS_STAT_MDI2)
1108 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3
1109 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
1110 + QCA808X_CDT_STATUS_STAT_MDI3)
1111 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
1112 + QCA808X_CDT_STATUS_STAT_MDI3)
1113 +
1114 +/* Added for reference of existence but should be handled by wait_for_completion already */
1115 +#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3))
1116 +
1117 +#define QCA808X_MMD7_LED_GLOBAL 0x8073
1118 +#define QCA808X_LED_BLINK_1 GENMASK(11, 6)
1119 +#define QCA808X_LED_BLINK_2 GENMASK(5, 0)
1120 +/* Values are the same for both BLINK_1 and BLINK_2 */
1121 +#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3)
1122 +#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
1123 +#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
1124 +#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
1125 +#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
1126 +#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
1127 +#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
1128 +#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
1129 +#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
1130 +#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0)
1131 +#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
1132 +#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
1133 +#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
1134 +#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
1135 +#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
1136 +#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
1137 +#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
1138 +#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
1139 +
1140 +#define QCA808X_MMD7_LED2_CTRL 0x8074
1141 +#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075
1142 +#define QCA808X_MMD7_LED1_CTRL 0x8076
1143 +#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077
1144 +#define QCA808X_MMD7_LED0_CTRL 0x8078
1145 +#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2))
1146 +
1147 +/* LED hw control pattern is the same for every LED */
1148 +#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0)
1149 +#define QCA808X_LED_SPEED2500_ON BIT(15)
1150 +#define QCA808X_LED_SPEED2500_BLINK BIT(14)
1151 +/* Follow blink trigger even if duplex or speed condition doesn't match */
1152 +#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13)
1153 +#define QCA808X_LED_FULL_DUPLEX_ON BIT(12)
1154 +#define QCA808X_LED_HALF_DUPLEX_ON BIT(11)
1155 +#define QCA808X_LED_TX_BLINK BIT(10)
1156 +#define QCA808X_LED_RX_BLINK BIT(9)
1157 +#define QCA808X_LED_TX_ON_10MS BIT(8)
1158 +#define QCA808X_LED_RX_ON_10MS BIT(7)
1159 +#define QCA808X_LED_SPEED1000_ON BIT(6)
1160 +#define QCA808X_LED_SPEED100_ON BIT(5)
1161 +#define QCA808X_LED_SPEED10_ON BIT(4)
1162 +#define QCA808X_LED_COLLISION_BLINK BIT(3)
1163 +#define QCA808X_LED_SPEED1000_BLINK BIT(2)
1164 +#define QCA808X_LED_SPEED100_BLINK BIT(1)
1165 +#define QCA808X_LED_SPEED10_BLINK BIT(0)
1166 +
1167 +#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079
1168 +#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2))
1169 +
1170 +/* LED force ctrl is the same for every LED
1171 + * No documentation exist for this, not even internal one
1172 + * with NDA as QCOM gives only info about configuring
1173 + * hw control pattern rules and doesn't indicate any way
1174 + * to force the LED to specific mode.
1175 + * These define comes from reverse and testing and maybe
1176 + * lack of some info or some info are not entirely correct.
1177 + * For the basic LED control and hw control these finding
1178 + * are enough to support LED control in all the required APIs.
1179 + *
1180 + * On doing some comparison with implementation with qca807x,
1181 + * it was found that it's 1:1 equal to it and confirms all the
1182 + * reverse done. It was also found further specification with the
1183 + * force mode and the blink modes.
1184 + */
1185 +#define QCA808X_LED_FORCE_EN BIT(15)
1186 +#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13)
1187 +#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
1188 +#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
1189 +#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
1190 +#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
1191 +
1192 +#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a
1193 +/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
1194 + * LED to active high. It's not clear what BIT 3 and BIT 4 does.
1195 + */
1196 +#define QCA808X_LED_ACTIVE_HIGH BIT(6)
1197 +
1198 +/* QCA808X 1G chip type */
1199 +#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
1200 +#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
1201 +
1202 +#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
1203 +#define QCA8081_PHY_FIFO_RSTN BIT(11)
1204 +
1205 +#define QCA8081_PHY_ID 0x004dd101
1206 +
1207 +MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
1208 +MODULE_AUTHOR("Matus Ujhelyi");
1209 +MODULE_LICENSE("GPL");
1210 +
1211 +struct qca808x_priv {
1212 + int led_polarity_mode;
1213 +};
1214 +
1215 +static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1216 +{
1217 + int ret;
1218 +
1219 + /* Enable fast retrain */
1220 + ret = genphy_c45_fast_retrain(phydev, true);
1221 + if (ret)
1222 + return ret;
1223 +
1224 + phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1225 + QCA808X_TOP_OPTION1_DATA);
1226 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1227 + QCA808X_MSE_THRESHOLD_20DB_VALUE);
1228 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1229 + QCA808X_MSE_THRESHOLD_17DB_VALUE);
1230 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1231 + QCA808X_MSE_THRESHOLD_27DB_VALUE);
1232 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1233 + QCA808X_MSE_THRESHOLD_28DB_VALUE);
1234 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1235 + QCA808X_MMD3_DEBUG_1_VALUE);
1236 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1237 + QCA808X_MMD3_DEBUG_4_VALUE);
1238 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1239 + QCA808X_MMD3_DEBUG_5_VALUE);
1240 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1241 + QCA808X_MMD3_DEBUG_3_VALUE);
1242 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1243 + QCA808X_MMD3_DEBUG_6_VALUE);
1244 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1245 + QCA808X_MMD3_DEBUG_2_VALUE);
1246 +
1247 + return 0;
1248 +}
1249 +
1250 +static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1251 +{
1252 + u16 seed_value;
1253 +
1254 + if (!enable)
1255 + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1256 + QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
1257 +
1258 + seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
1259 + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1260 + QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
1261 + FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
1262 + QCA808X_MASTER_SLAVE_SEED_ENABLE);
1263 +}
1264 +
1265 +static bool qca808x_is_prefer_master(struct phy_device *phydev)
1266 +{
1267 + return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
1268 + (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
1269 +}
1270 +
1271 +static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
1272 +{
1273 + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
1274 +}
1275 +
1276 +static int qca808x_probe(struct phy_device *phydev)
1277 +{
1278 + struct device *dev = &phydev->mdio.dev;
1279 + struct qca808x_priv *priv;
1280 +
1281 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1282 + if (!priv)
1283 + return -ENOMEM;
1284 +
1285 + /* Init LED polarity mode to -1 */
1286 + priv->led_polarity_mode = -1;
1287 +
1288 + phydev->priv = priv;
1289 +
1290 + return 0;
1291 +}
1292 +
1293 +static int qca808x_config_init(struct phy_device *phydev)
1294 +{
1295 + int ret;
1296 +
1297 + /* Active adc&vga on 802.3az for the link 1000M and 100M */
1298 + ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1299 + QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1300 + if (ret)
1301 + return ret;
1302 +
1303 + /* Adjust the threshold on 802.3az for the link 1000M */
1304 + ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1305 + QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
1306 + QCA808X_MMD3_AZ_TRAINING_VAL);
1307 + if (ret)
1308 + return ret;
1309 +
1310 + if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1311 + /* Config the fast retrain for the link 2500M */
1312 + ret = qca808x_phy_fast_retrain_config(phydev);
1313 + if (ret)
1314 + return ret;
1315 +
1316 + ret = genphy_read_master_slave(phydev);
1317 + if (ret < 0)
1318 + return ret;
1319 +
1320 + if (!qca808x_is_prefer_master(phydev)) {
1321 + /* Enable seed and configure lower ramdom seed to make phy
1322 + * linked as slave mode.
1323 + */
1324 + ret = qca808x_phy_ms_seed_enable(phydev, true);
1325 + if (ret)
1326 + return ret;
1327 + }
1328 + }
1329 +
1330 + /* Configure adc threshold as 100mv for the link 10M */
1331 + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1332 + QCA808X_ADC_THRESHOLD_MASK,
1333 + QCA808X_ADC_THRESHOLD_100MV);
1334 +}
1335 +
1336 +static int qca808x_read_status(struct phy_device *phydev)
1337 +{
1338 + struct at803x_ss_mask ss_mask = { 0 };
1339 + int ret;
1340 +
1341 + ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1342 + if (ret < 0)
1343 + return ret;
1344 +
1345 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
1346 + ret & MDIO_AN_10GBT_STAT_LP2_5G);
1347 +
1348 + ret = genphy_read_status(phydev);
1349 + if (ret)
1350 + return ret;
1351 +
1352 + /* qca8081 takes the different bits for speed value from at803x */
1353 + ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
1354 + ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
1355 + ret = at803x_read_specific_status(phydev, ss_mask);
1356 + if (ret < 0)
1357 + return ret;
1358 +
1359 + if (phydev->link) {
1360 + if (phydev->speed == SPEED_2500)
1361 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1362 + else
1363 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
1364 + } else {
1365 + /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1366 + * except for master/slave configuration fault detected or the master mode
1367 + * preferred.
1368 + *
1369 + * the reason for not putting this code into the function link_change_notify is
1370 + * the corner case where the link partner is also the qca8081 PHY and the seed
1371 + * value is configured as the same value, the link can't be up and no link change
1372 + * occurs.
1373 + */
1374 + if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1375 + if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
1376 + qca808x_is_prefer_master(phydev)) {
1377 + qca808x_phy_ms_seed_enable(phydev, false);
1378 + } else {
1379 + qca808x_phy_ms_seed_enable(phydev, true);
1380 + }
1381 + }
1382 + }
1383 +
1384 + return 0;
1385 +}
1386 +
1387 +static int qca808x_soft_reset(struct phy_device *phydev)
1388 +{
1389 + int ret;
1390 +
1391 + ret = genphy_soft_reset(phydev);
1392 + if (ret < 0)
1393 + return ret;
1394 +
1395 + if (qca808x_has_fast_retrain_or_slave_seed(phydev))
1396 + ret = qca808x_phy_ms_seed_enable(phydev, true);
1397 +
1398 + return ret;
1399 +}
1400 +
1401 +static bool qca808x_cdt_fault_length_valid(int cdt_code)
1402 +{
1403 + switch (cdt_code) {
1404 + case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
1405 + case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
1406 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
1407 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
1408 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
1409 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
1410 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
1411 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
1412 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
1413 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
1414 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
1415 + return true;
1416 + default:
1417 + return false;
1418 + }
1419 +}
1420 +
1421 +static int qca808x_cable_test_result_trans(int cdt_code)
1422 +{
1423 + switch (cdt_code) {
1424 + case QCA808X_CDT_STATUS_STAT_NORMAL:
1425 + return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1426 + case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
1427 + return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1428 + case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
1429 + return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1430 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
1431 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
1432 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
1433 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
1434 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
1435 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
1436 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
1437 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
1438 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
1439 + return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
1440 + case QCA808X_CDT_STATUS_STAT_FAIL:
1441 + default:
1442 + return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1443 + }
1444 +}
1445 +
1446 +static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
1447 + int result)
1448 +{
1449 + int val;
1450 + u32 cdt_length_reg = 0;
1451 +
1452 + switch (pair) {
1453 + case ETHTOOL_A_CABLE_PAIR_A:
1454 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
1455 + break;
1456 + case ETHTOOL_A_CABLE_PAIR_B:
1457 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
1458 + break;
1459 + case ETHTOOL_A_CABLE_PAIR_C:
1460 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
1461 + break;
1462 + case ETHTOOL_A_CABLE_PAIR_D:
1463 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
1464 + break;
1465 + default:
1466 + return -EINVAL;
1467 + }
1468 +
1469 + val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
1470 + if (val < 0)
1471 + return val;
1472 +
1473 + if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
1474 + val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
1475 + else
1476 + val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
1477 +
1478 + return at803x_cdt_fault_length(val);
1479 +}
1480 +
1481 +static int qca808x_cable_test_start(struct phy_device *phydev)
1482 +{
1483 + int ret;
1484 +
1485 + /* perform CDT with the following configs:
1486 + * 1. disable hibernation.
1487 + * 2. force PHY working in MDI mode.
1488 + * 3. for PHY working in 1000BaseT.
1489 + * 4. configure the threshold.
1490 + */
1491 +
1492 + ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
1493 + if (ret < 0)
1494 + return ret;
1495 +
1496 + ret = at803x_config_mdix(phydev, ETH_TP_MDI);
1497 + if (ret < 0)
1498 + return ret;
1499 +
1500 + /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
1501 + phydev->duplex = DUPLEX_FULL;
1502 + phydev->speed = SPEED_1000;
1503 + ret = genphy_c45_pma_setup_forced(phydev);
1504 + if (ret < 0)
1505 + return ret;
1506 +
1507 + ret = genphy_setup_forced(phydev);
1508 + if (ret < 0)
1509 + return ret;
1510 +
1511 + /* configure the thresholds for open, short, pair ok test */
1512 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
1513 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
1514 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
1515 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
1516 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
1517 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
1518 +
1519 + return 0;
1520 +}
1521 +
1522 +static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
1523 + u16 status)
1524 +{
1525 + int length, result;
1526 + u16 pair_code;
1527 +
1528 + switch (pair) {
1529 + case ETHTOOL_A_CABLE_PAIR_A:
1530 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
1531 + break;
1532 + case ETHTOOL_A_CABLE_PAIR_B:
1533 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
1534 + break;
1535 + case ETHTOOL_A_CABLE_PAIR_C:
1536 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
1537 + break;
1538 + case ETHTOOL_A_CABLE_PAIR_D:
1539 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
1540 + break;
1541 + default:
1542 + return -EINVAL;
1543 + }
1544 +
1545 + result = qca808x_cable_test_result_trans(pair_code);
1546 + ethnl_cable_test_result(phydev, pair, result);
1547 +
1548 + if (qca808x_cdt_fault_length_valid(pair_code)) {
1549 + length = qca808x_cdt_fault_length(phydev, pair, result);
1550 + ethnl_cable_test_fault_length(phydev, pair, length);
1551 + }
1552 +
1553 + return 0;
1554 +}
1555 +
1556 +static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
1557 +{
1558 + int ret, val;
1559 +
1560 + *finished = false;
1561 +
1562 + val = QCA808X_CDT_ENABLE_TEST |
1563 + QCA808X_CDT_LENGTH_UNIT;
1564 + ret = at803x_cdt_start(phydev, val);
1565 + if (ret)
1566 + return ret;
1567 +
1568 + ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
1569 + if (ret)
1570 + return ret;
1571 +
1572 + val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
1573 + if (val < 0)
1574 + return val;
1575 +
1576 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
1577 + if (ret)
1578 + return ret;
1579 +
1580 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
1581 + if (ret)
1582 + return ret;
1583 +
1584 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
1585 + if (ret)
1586 + return ret;
1587 +
1588 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
1589 + if (ret)
1590 + return ret;
1591 +
1592 + *finished = true;
1593 +
1594 + return 0;
1595 +}
1596 +
1597 +static int qca808x_get_features(struct phy_device *phydev)
1598 +{
1599 + int ret;
1600 +
1601 + ret = genphy_c45_pma_read_abilities(phydev);
1602 + if (ret)
1603 + return ret;
1604 +
1605 + /* The autoneg ability is not existed in bit3 of MMD7.1,
1606 + * but it is supported by qca808x PHY, so we add it here
1607 + * manually.
1608 + */
1609 + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1610 +
1611 + /* As for the qca8081 1G version chip, the 2500baseT ability is also
1612 + * existed in the bit0 of MMD1.21, we need to remove it manually if
1613 + * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
1614 + */
1615 + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
1616 + if (ret < 0)
1617 + return ret;
1618 +
1619 + if (QCA808X_PHY_CHIP_TYPE_1G & ret)
1620 + linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
1621 +
1622 + return 0;
1623 +}
1624 +
1625 +static int qca808x_config_aneg(struct phy_device *phydev)
1626 +{
1627 + int phy_ctrl = 0;
1628 + int ret;
1629 +
1630 + ret = at803x_prepare_config_aneg(phydev);
1631 + if (ret)
1632 + return ret;
1633 +
1634 + /* The reg MII_BMCR also needs to be configured for force mode, the
1635 + * genphy_config_aneg is also needed.
1636 + */
1637 + if (phydev->autoneg == AUTONEG_DISABLE)
1638 + genphy_c45_pma_setup_forced(phydev);
1639 +
1640 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
1641 + phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
1642 +
1643 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1644 + MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
1645 + if (ret < 0)
1646 + return ret;
1647 +
1648 + return __genphy_config_aneg(phydev, ret);
1649 +}
1650 +
1651 +static void qca808x_link_change_notify(struct phy_device *phydev)
1652 +{
1653 + /* Assert interface sgmii fifo on link down, deassert it on link up,
1654 + * the interface device address is always phy address added by 1.
1655 + */
1656 + mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
1657 + MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
1658 + QCA8081_PHY_FIFO_RSTN,
1659 + phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
1660 +}
1661 +
1662 +static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
1663 + u16 *offload_trigger)
1664 +{
1665 + /* Parsing specific to netdev trigger */
1666 + if (test_bit(TRIGGER_NETDEV_TX, &rules))
1667 + *offload_trigger |= QCA808X_LED_TX_BLINK;
1668 + if (test_bit(TRIGGER_NETDEV_RX, &rules))
1669 + *offload_trigger |= QCA808X_LED_RX_BLINK;
1670 + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
1671 + *offload_trigger |= QCA808X_LED_SPEED10_ON;
1672 + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
1673 + *offload_trigger |= QCA808X_LED_SPEED100_ON;
1674 + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
1675 + *offload_trigger |= QCA808X_LED_SPEED1000_ON;
1676 + if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
1677 + *offload_trigger |= QCA808X_LED_SPEED2500_ON;
1678 + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
1679 + *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
1680 + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
1681 + *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
1682 +
1683 + if (rules && !*offload_trigger)
1684 + return -EOPNOTSUPP;
1685 +
1686 + /* Enable BLINK_CHECK_BYPASS by default to make the LED
1687 + * blink even with duplex or speed mode not enabled.
1688 + */
1689 + *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
1690 +
1691 + return 0;
1692 +}
1693 +
1694 +static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
1695 +{
1696 + u16 reg;
1697 +
1698 + if (index > 2)
1699 + return -EINVAL;
1700 +
1701 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
1702 +
1703 + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
1704 + QCA808X_LED_FORCE_EN);
1705 +}
1706 +
1707 +static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
1708 + unsigned long rules)
1709 +{
1710 + u16 offload_trigger = 0;
1711 +
1712 + if (index > 2)
1713 + return -EINVAL;
1714 +
1715 + return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
1716 +}
1717 +
1718 +static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
1719 + unsigned long rules)
1720 +{
1721 + u16 reg, offload_trigger = 0;
1722 + int ret;
1723 +
1724 + if (index > 2)
1725 + return -EINVAL;
1726 +
1727 + reg = QCA808X_MMD7_LED_CTRL(index);
1728 +
1729 + ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
1730 + if (ret)
1731 + return ret;
1732 +
1733 + ret = qca808x_led_hw_control_enable(phydev, index);
1734 + if (ret)
1735 + return ret;
1736 +
1737 + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
1738 + QCA808X_LED_PATTERN_MASK,
1739 + offload_trigger);
1740 +}
1741 +
1742 +static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
1743 +{
1744 + u16 reg;
1745 + int val;
1746 +
1747 + if (index > 2)
1748 + return false;
1749 +
1750 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
1751 +
1752 + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
1753 +
1754 + return !(val & QCA808X_LED_FORCE_EN);
1755 +}
1756 +
1757 +static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
1758 + unsigned long *rules)
1759 +{
1760 + u16 reg;
1761 + int val;
1762 +
1763 + if (index > 2)
1764 + return -EINVAL;
1765 +
1766 + /* Check if we have hw control enabled */
1767 + if (qca808x_led_hw_control_status(phydev, index))
1768 + return -EINVAL;
1769 +
1770 + reg = QCA808X_MMD7_LED_CTRL(index);
1771 +
1772 + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
1773 + if (val & QCA808X_LED_TX_BLINK)
1774 + set_bit(TRIGGER_NETDEV_TX, rules);
1775 + if (val & QCA808X_LED_RX_BLINK)
1776 + set_bit(TRIGGER_NETDEV_RX, rules);
1777 + if (val & QCA808X_LED_SPEED10_ON)
1778 + set_bit(TRIGGER_NETDEV_LINK_10, rules);
1779 + if (val & QCA808X_LED_SPEED100_ON)
1780 + set_bit(TRIGGER_NETDEV_LINK_100, rules);
1781 + if (val & QCA808X_LED_SPEED1000_ON)
1782 + set_bit(TRIGGER_NETDEV_LINK_1000, rules);
1783 + if (val & QCA808X_LED_SPEED2500_ON)
1784 + set_bit(TRIGGER_NETDEV_LINK_2500, rules);
1785 + if (val & QCA808X_LED_HALF_DUPLEX_ON)
1786 + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
1787 + if (val & QCA808X_LED_FULL_DUPLEX_ON)
1788 + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
1789 +
1790 + return 0;
1791 +}
1792 +
1793 +static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
1794 +{
1795 + u16 reg;
1796 +
1797 + if (index > 2)
1798 + return -EINVAL;
1799 +
1800 + reg = QCA808X_MMD7_LED_CTRL(index);
1801 +
1802 + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
1803 + QCA808X_LED_PATTERN_MASK);
1804 +}
1805 +
1806 +static int qca808x_led_brightness_set(struct phy_device *phydev,
1807 + u8 index, enum led_brightness value)
1808 +{
1809 + u16 reg;
1810 + int ret;
1811 +
1812 + if (index > 2)
1813 + return -EINVAL;
1814 +
1815 + if (!value) {
1816 + ret = qca808x_led_hw_control_reset(phydev, index);
1817 + if (ret)
1818 + return ret;
1819 + }
1820 +
1821 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
1822 +
1823 + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
1824 + QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
1825 + QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
1826 + QCA808X_LED_FORCE_OFF);
1827 +}
1828 +
1829 +static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
1830 + unsigned long *delay_on,
1831 + unsigned long *delay_off)
1832 +{
1833 + int ret;
1834 + u16 reg;
1835 +
1836 + if (index > 2)
1837 + return -EINVAL;
1838 +
1839 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
1840 +
1841 + /* Set blink to 50% off, 50% on at 4Hz by default */
1842 + ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
1843 + QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
1844 + QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
1845 + if (ret)
1846 + return ret;
1847 +
1848 + /* We use BLINK_1 for normal blinking */
1849 + ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
1850 + QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
1851 + QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
1852 + if (ret)
1853 + return ret;
1854 +
1855 + /* We set blink to 4Hz, aka 250ms */
1856 + *delay_on = 250 / 2;
1857 + *delay_off = 250 / 2;
1858 +
1859 + return 0;
1860 +}
1861 +
1862 +static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
1863 + unsigned long modes)
1864 +{
1865 + struct qca808x_priv *priv = phydev->priv;
1866 + bool active_low = false;
1867 + u32 mode;
1868 +
1869 + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
1870 + switch (mode) {
1871 + case PHY_LED_ACTIVE_LOW:
1872 + active_low = true;
1873 + break;
1874 + default:
1875 + return -EINVAL;
1876 + }
1877 + }
1878 +
1879 + /* PHY polarity is global and can't be set per LED.
1880 + * To detect this, check if last requested polarity mode
1881 + * match the new one.
1882 + */
1883 + if (priv->led_polarity_mode >= 0 &&
1884 + priv->led_polarity_mode != active_low) {
1885 + phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
1886 + return -EINVAL;
1887 + }
1888 +
1889 + /* Save the last PHY polarity mode */
1890 + priv->led_polarity_mode = active_low;
1891 +
1892 + return phy_modify_mmd(phydev, MDIO_MMD_AN,
1893 + QCA808X_MMD7_LED_POLARITY_CTRL,
1894 + QCA808X_LED_ACTIVE_HIGH,
1895 + active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
1896 +}
1897 +
1898 +static struct phy_driver qca808x_driver[] = {
1899 +{
1900 + /* Qualcomm QCA8081 */
1901 + PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
1902 + .name = "Qualcomm QCA8081",
1903 + .flags = PHY_POLL_CABLE_TEST,
1904 + .probe = qca808x_probe,
1905 + .config_intr = at803x_config_intr,
1906 + .handle_interrupt = at803x_handle_interrupt,
1907 + .get_tunable = at803x_get_tunable,
1908 + .set_tunable = at803x_set_tunable,
1909 + .set_wol = at803x_set_wol,
1910 + .get_wol = at803x_get_wol,
1911 + .get_features = qca808x_get_features,
1912 + .config_aneg = qca808x_config_aneg,
1913 + .suspend = genphy_suspend,
1914 + .resume = genphy_resume,
1915 + .read_status = qca808x_read_status,
1916 + .config_init = qca808x_config_init,
1917 + .soft_reset = qca808x_soft_reset,
1918 + .cable_test_start = qca808x_cable_test_start,
1919 + .cable_test_get_status = qca808x_cable_test_get_status,
1920 + .link_change_notify = qca808x_link_change_notify,
1921 + .led_brightness_set = qca808x_led_brightness_set,
1922 + .led_blink_set = qca808x_led_blink_set,
1923 + .led_hw_is_supported = qca808x_led_hw_is_supported,
1924 + .led_hw_control_set = qca808x_led_hw_control_set,
1925 + .led_hw_control_get = qca808x_led_hw_control_get,
1926 + .led_polarity_set = qca808x_led_polarity_set,
1927 +}, };
1928 +
1929 +module_phy_driver(qca808x_driver);
1930 +
1931 +static struct mdio_device_id __maybe_unused qca808x_tbl[] = {
1932 + { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
1933 + { }
1934 +};
1935 +
1936 +MODULE_DEVICE_TABLE(mdio, qca808x_tbl);
Staging tree of Chuanhong Guo