projects / openwrt / staging / blocktrron.git / blob
? search:


5cf09039dfa9ca4e0420ec20575fa817b10fb1fc
[openwrt/staging/blocktrron.git] /
1 From 2a07ee2b9608e665872e7d83bebd3acb7e45c2e6 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Sat, 9 Nov 2019 15:02:51 +0200
4 Subject: [PATCH] net: mscc: ocelot: change prototypes of switchdev port
5 attribute handlers
6
7 This is needed so that the Felix DSA front-end can call the Ocelot
8 implementations.
9
10 The implementation of the "mc_disabled" switchdev attribute has also
11 been simplified by using the read-modify-write macro instead of
12 open-coding that operation.
13
14 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
15 Signed-off-by: David S. Miller <davem@davemloft.net>
16 ---
17 drivers/net/ethernet/mscc/ocelot.c | 88 +++++++++++++++++++-------------------
18 1 file changed, 45 insertions(+), 43 deletions(-)
19
20 --- a/drivers/net/ethernet/mscc/ocelot.c
21 +++ b/drivers/net/ethernet/mscc/ocelot.c
22 @@ -1285,26 +1285,20 @@ static const struct ethtool_ops ocelot_e
23 .get_ts_info = ocelot_get_ts_info,
24 };
25
26 -static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
27 - struct switchdev_trans *trans,
28 - u8 state)
29 +static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
30 + u8 state)
31 {
32 - struct ocelot *ocelot = ocelot_port->ocelot;
33 u32 port_cfg;
34 - int port, i;
35 -
36 - if (switchdev_trans_ph_prepare(trans))
37 - return 0;
38 + int p, i;
39
40 - if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
41 - return 0;
42 + if (!(BIT(port) & ocelot->bridge_mask))
43 + return;
44
45 - port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
46 - ocelot_port->chip_port);
47 + port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
48
49 switch (state) {
50 case BR_STATE_FORWARDING:
51 - ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
52 + ocelot->bridge_fwd_mask |= BIT(port);
53 /* Fallthrough */
54 case BR_STATE_LEARNING:
55 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
56 @@ -1312,19 +1306,18 @@ static int ocelot_port_attr_stp_state_se
57
58 default:
59 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
60 - ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
61 + ocelot->bridge_fwd_mask &= ~BIT(port);
62 break;
63 }
64
65 - ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
66 - ocelot_port->chip_port);
67 + ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
68
69 /* Apply FWD mask. The loop is needed to add/remove the current port as
70 * a source for the other ports.
71 */
72 - for (port = 0; port < ocelot->num_phys_ports; port++) {
73 - if (ocelot->bridge_fwd_mask & BIT(port)) {
74 - unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
75 + for (p = 0; p < ocelot->num_phys_ports; p++) {
76 + if (ocelot->bridge_fwd_mask & BIT(p)) {
77 + unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
78
79 for (i = 0; i < ocelot->num_phys_ports; i++) {
80 unsigned long bond_mask = ocelot->lags[i];
81 @@ -1332,7 +1325,7 @@ static int ocelot_port_attr_stp_state_se
82 if (!bond_mask)
83 continue;
84
85 - if (bond_mask & BIT(port)) {
86 + if (bond_mask & BIT(p)) {
87 mask &= ~bond_mask;
88 break;
89 }
90 @@ -1340,47 +1333,55 @@ static int ocelot_port_attr_stp_state_se
91
92 ocelot_write_rix(ocelot,
93 BIT(ocelot->num_phys_ports) | mask,
94 - ANA_PGID_PGID, PGID_SRC + port);
95 + ANA_PGID_PGID, PGID_SRC + p);
96 } else {
97 /* Only the CPU port, this is compatible with link
98 * aggregation.
99 */
100 ocelot_write_rix(ocelot,
101 BIT(ocelot->num_phys_ports),
102 - ANA_PGID_PGID, PGID_SRC + port);
103 + ANA_PGID_PGID, PGID_SRC + p);
104 }
105 }
106 +}
107 +
108 +static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
109 + struct switchdev_trans *trans,
110 + u8 state)
111 +{
112 + if (switchdev_trans_ph_prepare(trans))
113 + return;
114
115 - return 0;
116 + ocelot_bridge_stp_state_set(ocelot, port, state);
117 }
118
119 -static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
120 +static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
121 +{
122 + ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2),
123 + ANA_AUTOAGE);
124 +}
125 +
126 +static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
127 unsigned long ageing_clock_t)
128 {
129 - struct ocelot *ocelot = ocelot_port->ocelot;
130 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
131 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
132
133 - ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
134 - ANA_AUTOAGE);
135 + ocelot_set_ageing_time(ocelot, ageing_time);
136 }
137
138 -static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
139 +static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc)
140 {
141 - struct ocelot *ocelot = port->ocelot;
142 - u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
143 - port->chip_port);
144 + u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
145 + ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
146 + ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
147 + u32 val = 0;
148
149 if (mc)
150 - val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
151 - ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
152 - ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
153 - else
154 - val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
155 - ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
156 - ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
157 + val = cpu_fwd_mcast;
158
159 - ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
160 + ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast,
161 + ANA_PORT_CPU_FWD_CFG, port);
162 }
163
164 static int ocelot_port_attr_set(struct net_device *dev,
165 @@ -1389,22 +1390,23 @@ static int ocelot_port_attr_set(struct n
166 {
167 struct ocelot_port *ocelot_port = netdev_priv(dev);
168 struct ocelot *ocelot = ocelot_port->ocelot;
169 + int port = ocelot_port->chip_port;
170 int err = 0;
171
172 switch (attr->id) {
173 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
174 - ocelot_port_attr_stp_state_set(ocelot_port, trans,
175 + ocelot_port_attr_stp_state_set(ocelot, port, trans,
176 attr->u.stp_state);
177 break;
178 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
179 - ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
180 + ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time);
181 break;
182 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
183 - ocelot_port_vlan_filtering(ocelot, ocelot_port->chip_port,
184 + ocelot_port_vlan_filtering(ocelot, port,
185 attr->u.vlan_filtering);
186 break;
187 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
188 - ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
189 + ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled);
190 break;
191 default:
192 err = -EOPNOTSUPP;
Staging tree of David Bauer