5dad164e3c280f1a32215f4af92be1b10a8082e2
[openwrt/staging/stintel.git] /
1 From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Thu, 7 Jul 2022 03:09:35 +0200
4 Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin
5 definition
6
7 Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
8 pins and rgmii2 pins for ipq8064.
9
10 Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064
11 dtsi.
12
13 Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to
14 ipq8064 dtsi.
15
16 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
17 Tested-by: Jonathan McDowell <noodles@earth.li>
18 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
19 Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com
20 ---
21 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -----
22 arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 -------
23 arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++
24 3 files changed, 32 insertions(+), 15 deletions(-)
25
26 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
27 +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
28 @@ -305,15 +305,6 @@
29 };
30 };
31
32 - mdio0_pins: mdio0_pins {
33 - mux {
34 - pins = "gpio0", "gpio1";
35 - function = "gpio";
36 - drive-strength = <8>;
37 - bias-disable;
38 - };
39 - };
40 -
41 mdio1_pins: mdio1_pins {
42 mux {
43 pins = "gpio10", "gpio11";
44 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
45 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
46 @@ -382,6 +382,13 @@
47 };
48 };
49
50 + i2c4_pins: i2c4-default {
51 + pins = "gpio12", "gpio13";
52 + function = "gsbi4";
53 + drive-strength = <12>;
54 + bias-disable;
55 + };
56 +
57 spi_pins: spi_pins {
58 mux {
59 pins = "gpio18", "gpio19", "gpio21";
60 @@ -424,6 +431,8 @@
61
62 pullups {
63 pins = "gpio39";
64 + function = "nand";
65 + drive-strength = <10>;
66 bias-pull-up;
67 };
68
69 @@ -431,9 +440,32 @@
70 pins = "gpio40", "gpio41", "gpio42",
71 "gpio43", "gpio44", "gpio45",
72 "gpio46", "gpio47";
73 + function = "nand";
74 + drive-strength = <10>;
75 bias-bus-hold;
76 };
77 };
78 +
79 + mdio0_pins: mdio0-pins {
80 + mux {
81 + pins = "gpio0", "gpio1";
82 + function = "mdio";
83 + drive-strength = <8>;
84 + bias-disable;
85 + };
86 + };
87 +
88 + rgmii2_pins: rgmii2-pins {
89 + mux {
90 + pins = "gpio27", "gpio28", "gpio29",
91 + "gpio30", "gpio31", "gpio32",
92 + "gpio51", "gpio52", "gpio59",
93 + "gpio60", "gpio61", "gpio62";
94 + function = "rgmii2";
95 + drive-strength = <8>;
96 + bias-disable;
97 + };
98 + };
99 };
100
101 intc: interrupt-controller@2000000 {