git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 8df9fefd1d04f6f97f6015d7347104f69e6ea580 Mon Sep 17 00:00:00 2001
   2 From: Baruch Siach <baruch.siach@siklu.com>
   3 Date: Tue, 21 Jun 2022 11:54:52 +0300
   4 Subject: [PATCH] PCI: dwc: Move GEN3_RELATED DBI definitions to common header
   5
   6 These are common dwc macros that will be used for other platforms.
   7
   8 Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il
   9 Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  10 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  11 Reviewed-by: Rob Herring <robh@kernel.org>
  12 ---
  13  drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
  14  drivers/pci/controller/dwc/pcie-tegra194.c   | 6 ------
  15  2 files changed, 6 insertions(+), 6 deletions(-)
  16
  17 --- a/drivers/pci/controller/dwc/pcie-designware.h
  18 +++ b/drivers/pci/controller/dwc/pcie-designware.h
  19 @@ -74,6 +74,12 @@
  20  #define PCIE_MSI_INTR0_MASK            0x82C
  21  #define PCIE_MSI_INTR0_STATUS          0x830
  22
  23 +#define GEN3_RELATED_OFF                       0x890
  24 +#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL   BIT(0)
  25 +#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE       BIT(16)
  26 +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
  27 +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK  GENMASK(25, 24)
  28 +
  29  #define PCIE_PORT_MULTI_LANE_CTRL      0x8C0
  30  #define PORT_MLTI_UPCFG_SUPPORT                BIT(7)
  31
  32 --- a/drivers/pci/controller/dwc/pcie-tegra194.c
  33 +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
  34 @@ -193,12 +193,6 @@
  35  #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK  GENMASK(23, 8)
  36  #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK       GENMASK(3, 0)
  37
  38 -#define GEN3_RELATED_OFF                       0x890
  39 -#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL   BIT(0)
  40 -#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE       BIT(16)
  41 -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
  42 -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK  GENMASK(25, 24)
  43 -
  44  #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
  45  #define AMBA_ERROR_RESPONSE_CRS_SHIFT          3
  46  #define AMBA_ERROR_RESPONSE_CRS_MASK           GENMASK(1, 0)