63c25304a06cdcd35c0d098aa62485b19d78a5e7
[openwrt/staging/blocktrron.git] /
1 From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 19 Jul 2023 17:17:27 +0800
4 Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support
5 GMAC/USB3 Co-PHY
6
7 This patch adds infracfg to eth node to support enabling GMAC2.
8
9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
10 ---
11 arch/arm/dts/mt7981.dtsi | 7 +++++++
12 1 file changed, 7 insertions(+)
13
14 --- a/arch/arm/dts/mt7981.dtsi
15 +++ b/arch/arm/dts/mt7981.dtsi
16 @@ -266,6 +266,7 @@
17 reset-names = "fe";
18 mediatek,ethsys = <&ethsys>;
19 mediatek,sgmiisys = <&sgmiisys0>;
20 + mediatek,infracfg = <&topmisc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 status = "disabled";
24 @@ -284,6 +285,12 @@
25 #clock-cells = <1>;
26 };
27
28 + topmisc: topmisc@11d10000 {
29 + compatible = "mediatek,mt7981-topmisc", "syscon";
30 + reg = <0x11d10000 0x10000>;
31 + #clock-cells = <1>;
32 + };
33 +
34 spi0: spi@1100a000 {
35 compatible = "mediatek,ipm-spi";
36 reg = <0x1100a000 0x100>;