git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From: Lorenzo Bianconi <lorenzo@kernel.org>
   2 Date: Thu, 17 Nov 2022 15:29:53 +0100
   3 Subject: [PATCH] net: ethernet: mtk_eth_soc: fix RSTCTRL_PPE{0,1} definitions
   4
   5 Fix RSTCTRL_PPE0 and RSTCTRL_PPE1 register mask definitions for
   6 MTK_NETSYS_V2.
   7 Remove duplicated definitions.
   8
   9 Fixes: 160d3a9b1929 ("net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support")
  10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  11 Signed-off-by: David S. Miller <davem@davemloft.net>
  12 ---
  13
  14 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  15 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  16 @@ -3238,16 +3238,17 @@ static int mtk_hw_init(struct mtk_eth *e
  17                 return 0;
  18         }
  19
  20 -       val = RSTCTRL_FE | RSTCTRL_PPE;
  21         if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  22                 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  23 -
  24 -               val |= RSTCTRL_ETH;
  25 -               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  26 -                       val |= RSTCTRL_PPE1;
  27 +               val = RSTCTRL_PPE0_V2;
  28 +       } else {
  29 +               val = RSTCTRL_PPE0;
  30         }
  31
  32 -       ethsys_reset(eth, val);
  33 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  34 +               val |= RSTCTRL_PPE1;
  35 +
  36 +       ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  37
  38         if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  39                 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  40 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  41 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  42 @@ -444,18 +444,14 @@
  43  /* ethernet reset control register */
  44  #define ETHSYS_RSTCTRL                 0x34
  45  #define RSTCTRL_FE                     BIT(6)
  46 -#define RSTCTRL_PPE                    BIT(31)
  47 -#define RSTCTRL_PPE1                   BIT(30)
  48 +#define RSTCTRL_PPE0                   BIT(31)
  49 +#define RSTCTRL_PPE0_V2                        BIT(30)
  50 +#define RSTCTRL_PPE1                   BIT(31)
  51  #define RSTCTRL_ETH                    BIT(23)
  52
  53  /* ethernet reset check idle register */
  54  #define ETHSYS_FE_RST_CHK_IDLE_EN      0x28
  55
  56 -/* ethernet reset control register */
  57 -#define ETHSYS_RSTCTRL         0x34
  58 -#define RSTCTRL_FE             BIT(6)
  59 -#define RSTCTRL_PPE            BIT(31)
  60 -
  61  /* ethernet dma channel agent map */
  62  #define ETHSYS_DMA_AG_MAP      0x408
  63  #define ETHSYS_DMA_AG_MAP_PDMA BIT(0)