git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 77b0e8ded57e7fb5d742fb533d7a9bb3f3788513 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Wed, 13 Jan 2021 11:20:08 +0100
   4 Subject: [PATCH] drm/vc4: hdmi: Replace CSC_CTL hardcoded value by
   5  defines
   6
   7 On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an
   8 opaque value. Let's replace it with properly defined values.
   9
  10 Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
  11 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_hdmi.c | 5 ++---
  14  drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
  15  2 files changed, 5 insertions(+), 3 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  19 @@ -786,9 +786,8 @@ static void vc5_hdmi_csc_setup(struct vc
  20                                const struct drm_display_mode *mode)
  21  {
  22         unsigned long flags;
  23 -       u32 csc_ctl;
  24 -
  25 -       csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
  26 +       u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
  27 +                                                              VC5_MT_CP_CSC_CTL_MODE);
  28
  29         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
  30
  31 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  32 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  33 @@ -796,6 +796,9 @@ enum {
  34  # define VC4_HD_CSC_CTL_RGB2YCC                        BIT(1)
  35  # define VC4_HD_CSC_CTL_ENABLE                 BIT(0)
  36
  37 +# define VC5_MT_CP_CSC_CTL_ENABLE              BIT(2)
  38 +# define VC5_MT_CP_CSC_CTL_MODE_MASK           VC4_MASK(1, 0)
  39 +
  40  # define VC4_DVP_HT_CLOCK_STOP_PIXEL           BIT(1)
  41
  42  /* HVS display list information. */