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1 From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sat, 26 Feb 2022 14:52:26 +0100
4 Subject: [PATCH 06/14] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
5
6 Use ARRAY_SIZE for num_parents instead of hardcoding the value.
7
8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
9 Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
10 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
11 Tested-by: Jonathan McDowell <noodles@earth.li>
12 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
13 Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com
14 ---
15 drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++-----------------
16 1 file changed, 34 insertions(+), 34 deletions(-)
17
18 --- a/drivers/clk/qcom/gcc-ipq806x.c
19 +++ b/drivers/clk/qcom/gcc-ipq806x.c
20 @@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = {
21 .hw.init = &(struct clk_init_data){
22 .name = "gsbi1_uart_src",
23 .parent_data = gcc_pxo_pll8,
24 - .num_parents = 2,
25 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
26 .ops = &clk_rcg_ops,
27 .flags = CLK_SET_PARENT_GATE,
28 },
29 @@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = {
30 .hw.init = &(struct clk_init_data){
31 .name = "gsbi2_uart_src",
32 .parent_data = gcc_pxo_pll8,
33 - .num_parents = 2,
34 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
35 .ops = &clk_rcg_ops,
36 .flags = CLK_SET_PARENT_GATE,
37 },
38 @@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = {
39 .hw.init = &(struct clk_init_data){
40 .name = "gsbi4_uart_src",
41 .parent_data = gcc_pxo_pll8,
42 - .num_parents = 2,
43 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
44 .ops = &clk_rcg_ops,
45 .flags = CLK_SET_PARENT_GATE,
46 },
47 @@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = {
48 .hw.init = &(struct clk_init_data){
49 .name = "gsbi5_uart_src",
50 .parent_data = gcc_pxo_pll8,
51 - .num_parents = 2,
52 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
53 .ops = &clk_rcg_ops,
54 .flags = CLK_SET_PARENT_GATE,
55 },
56 @@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = {
57 .hw.init = &(struct clk_init_data){
58 .name = "gsbi6_uart_src",
59 .parent_data = gcc_pxo_pll8,
60 - .num_parents = 2,
61 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
62 .ops = &clk_rcg_ops,
63 .flags = CLK_SET_PARENT_GATE,
64 },
65 @@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = {
66 .hw.init = &(struct clk_init_data){
67 .name = "gsbi7_uart_src",
68 .parent_data = gcc_pxo_pll8,
69 - .num_parents = 2,
70 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
71 .ops = &clk_rcg_ops,
72 .flags = CLK_SET_PARENT_GATE,
73 },
74 @@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = {
75 .hw.init = &(struct clk_init_data){
76 .name = "gsbi1_qup_src",
77 .parent_data = gcc_pxo_pll8,
78 - .num_parents = 2,
79 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
80 .ops = &clk_rcg_ops,
81 .flags = CLK_SET_PARENT_GATE,
82 },
83 @@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = {
84 .hw.init = &(struct clk_init_data){
85 .name = "gsbi2_qup_src",
86 .parent_data = gcc_pxo_pll8,
87 - .num_parents = 2,
88 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
89 .ops = &clk_rcg_ops,
90 .flags = CLK_SET_PARENT_GATE,
91 },
92 @@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = {
93 .hw.init = &(struct clk_init_data){
94 .name = "gsbi4_qup_src",
95 .parent_data = gcc_pxo_pll8,
96 - .num_parents = 2,
97 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
98 .ops = &clk_rcg_ops,
99 .flags = CLK_SET_PARENT_GATE,
100 },
101 @@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = {
102 .hw.init = &(struct clk_init_data){
103 .name = "gsbi5_qup_src",
104 .parent_data = gcc_pxo_pll8,
105 - .num_parents = 2,
106 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
107 .ops = &clk_rcg_ops,
108 .flags = CLK_SET_PARENT_GATE,
109 },
110 @@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = {
111 .hw.init = &(struct clk_init_data){
112 .name = "gsbi6_qup_src",
113 .parent_data = gcc_pxo_pll8,
114 - .num_parents = 2,
115 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
116 .ops = &clk_rcg_ops,
117 .flags = CLK_SET_PARENT_GATE,
118 },
119 @@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = {
120 .hw.init = &(struct clk_init_data){
121 .name = "gsbi7_qup_src",
122 .parent_data = gcc_pxo_pll8,
123 - .num_parents = 2,
124 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
125 .ops = &clk_rcg_ops,
126 .flags = CLK_SET_PARENT_GATE,
127 },
128 @@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = {
129 .hw.init = &(struct clk_init_data){
130 .name = "gp0_src",
131 .parent_data = gcc_pxo_pll8_cxo,
132 - .num_parents = 3,
133 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
134 .ops = &clk_rcg_ops,
135 .flags = CLK_SET_PARENT_GATE,
136 },
137 @@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = {
138 .hw.init = &(struct clk_init_data){
139 .name = "gp1_src",
140 .parent_data = gcc_pxo_pll8_cxo,
141 - .num_parents = 3,
142 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
143 .ops = &clk_rcg_ops,
144 .flags = CLK_SET_RATE_GATE,
145 },
146 @@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = {
147 .hw.init = &(struct clk_init_data){
148 .name = "gp2_src",
149 .parent_data = gcc_pxo_pll8_cxo,
150 - .num_parents = 3,
151 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
152 .ops = &clk_rcg_ops,
153 .flags = CLK_SET_RATE_GATE,
154 },
155 @@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = {
156 .hw.init = &(struct clk_init_data){
157 .name = "prng_src",
158 .parent_data = gcc_pxo_pll8,
159 - .num_parents = 2,
160 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
161 .ops = &clk_rcg_ops,
162 },
163 },
164 @@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = {
165 .hw.init = &(struct clk_init_data){
166 .name = "sdc1_src",
167 .parent_data = gcc_pxo_pll8,
168 - .num_parents = 2,
169 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
170 .ops = &clk_rcg_ops,
171 },
172 }
173 @@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = {
174 .hw.init = &(struct clk_init_data){
175 .name = "sdc3_src",
176 .parent_data = gcc_pxo_pll8,
177 - .num_parents = 2,
178 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
179 .ops = &clk_rcg_ops,
180 },
181 }
182 @@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = {
183 .hw.init = &(struct clk_init_data){
184 .name = "tsif_ref_src",
185 .parent_data = gcc_pxo_pll8,
186 - .num_parents = 2,
187 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
188 .ops = &clk_rcg_ops,
189 },
190 }
191 @@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = {
192 .hw.init = &(struct clk_init_data){
193 .name = "pcie_ref_src",
194 .parent_data = gcc_pxo_pll3,
195 - .num_parents = 2,
196 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
197 .ops = &clk_rcg_ops,
198 .flags = CLK_SET_RATE_GATE,
199 },
200 @@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = {
201 .hw.init = &(struct clk_init_data){
202 .name = "pcie1_ref_src",
203 .parent_data = gcc_pxo_pll3,
204 - .num_parents = 2,
205 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
206 .ops = &clk_rcg_ops,
207 .flags = CLK_SET_RATE_GATE,
208 },
209 @@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = {
210 .hw.init = &(struct clk_init_data){
211 .name = "pcie2_ref_src",
212 .parent_data = gcc_pxo_pll3,
213 - .num_parents = 2,
214 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
215 .ops = &clk_rcg_ops,
216 .flags = CLK_SET_RATE_GATE,
217 },
218 @@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = {
219 .hw.init = &(struct clk_init_data){
220 .name = "sata_ref_src",
221 .parent_data = gcc_pxo_pll3,
222 - .num_parents = 2,
223 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
224 .ops = &clk_rcg_ops,
225 .flags = CLK_SET_RATE_GATE,
226 },
227 @@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_s
228 .hw.init = &(struct clk_init_data){
229 .name = "usb30_master_ref_src",
230 .parent_data = gcc_pxo_pll8_pll0,
231 - .num_parents = 3,
232 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
233 .ops = &clk_rcg_ops,
234 .flags = CLK_SET_RATE_GATE,
235 },
236 @@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = {
237 .hw.init = &(struct clk_init_data){
238 .name = "usb30_utmi_clk",
239 .parent_data = gcc_pxo_pll8_pll0,
240 - .num_parents = 3,
241 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
242 .ops = &clk_rcg_ops,
243 .flags = CLK_SET_RATE_GATE,
244 },
245 @@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
246 .hw.init = &(struct clk_init_data){
247 .name = "usb_hs1_xcvr_src",
248 .parent_data = gcc_pxo_pll8_pll0,
249 - .num_parents = 3,
250 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
251 .ops = &clk_rcg_ops,
252 .flags = CLK_SET_RATE_GATE,
253 },
254 @@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
255 .hw.init = &(struct clk_init_data){
256 .name = "usb_fs1_xcvr_src",
257 .parent_data = gcc_pxo_pll8_pll0,
258 - .num_parents = 3,
259 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
260 .ops = &clk_rcg_ops,
261 .flags = CLK_SET_RATE_GATE,
262 },
263 @@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src
264 .hw.init = &(struct clk_init_data){
265 .name = "gmac_core1_src",
266 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
267 - .num_parents = 5,
268 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
269 .ops = &clk_dyn_rcg_ops,
270 },
271 },
272 @@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src
273 .hw.init = &(struct clk_init_data){
274 .name = "gmac_core2_src",
275 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
276 - .num_parents = 5,
277 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
278 .ops = &clk_dyn_rcg_ops,
279 },
280 },
281 @@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src
282 .hw.init = &(struct clk_init_data){
283 .name = "gmac_core3_src",
284 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
285 - .num_parents = 5,
286 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
287 .ops = &clk_dyn_rcg_ops,
288 },
289 },
290 @@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src
291 .hw.init = &(struct clk_init_data){
292 .name = "gmac_core4_src",
293 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
294 - .num_parents = 5,
295 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
296 .ops = &clk_dyn_rcg_ops,
297 },
298 },
299 @@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src =
300 .hw.init = &(struct clk_init_data){
301 .name = "nss_tcm_src",
302 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
303 - .num_parents = 5,
304 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
305 .ops = &clk_dyn_rcg_ops,
306 },
307 },
308 @@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
309 .hw.init = &(struct clk_init_data){
310 .name = "ubi32_core1_src_clk",
311 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
312 - .num_parents = 5,
313 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
314 .ops = &clk_dyn_rcg_ops,
315 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
316 },
317 @@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
318 .hw.init = &(struct clk_init_data){
319 .name = "ubi32_core2_src_clk",
320 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
321 - .num_parents = 5,
322 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
323 .ops = &clk_dyn_rcg_ops,
324 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
325 },
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