git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 6f92d02f7af5a9b5ed5ded7dbeb18bf2bbb2ad85 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.org>
   3 Date: Tue, 24 Feb 2015 13:40:50 +0000
   4 Subject: [PATCH] pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 and
   5  46-53
   6
   7 Contrary to the documentation, the BCM2835 GPIO controller actually has
   8 four interrupt lines - one each for the three IRQ groups and one common. Rather
   9 confusingly, the GPIO interrupt groups don't correspond directly with the GPIO
  10 control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 GPIO1 and
  11 46-53 GPIO2.
  12
  13 Awkwardly, the GPIOS for IRQ GPIO1 straddle two 32-entry GPIO banks, so it is
  14 cleaner to split out a function to process the interrupts for a single GPIO
  15 bank.
  16
  17 This bug has only just been observed because GPIOs above 27 can only be
  18 accessed on an old Raspberry Pi with the optional P5 header fitted, where
  19 the pins are often used for I2S instead.
  20 ---
  21  drivers/pinctrl/bcm/pinctrl-bcm2835.c | 51 ++++++++++++++++++++++++++---------
  22  1 file changed, 39 insertions(+), 12 deletions(-)
  23
  24 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
  25 +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
  26 @@ -47,6 +47,7 @@
  27  #define MODULE_NAME "pinctrl-bcm2835"
  28  #define BCM2835_NUM_GPIOS 54
  29  #define BCM2835_NUM_BANKS 2
  30 +#define BCM2835_NUM_IRQS  3
  31
  32  #define BCM2835_PIN_BITMAP_SZ \
  33         DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
  34 @@ -82,13 +83,13 @@ enum bcm2835_pinconf_param {
  35
  36  struct bcm2835_gpio_irqdata {
  37         struct bcm2835_pinctrl *pc;
  38 -       int bank;
  39 +       int irqgroup;
  40  };
  41
  42  struct bcm2835_pinctrl {
  43         struct device *dev;
  44         void __iomem *base;
  45 -       int irq[BCM2835_NUM_BANKS];
  46 +       int irq[BCM2835_NUM_IRQS];
  47
  48         /* note: locking assumes each bank will have its own unsigned long */
  49         unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
  50 @@ -99,7 +100,7 @@ struct bcm2835_pinctrl {
  51         struct gpio_chip gpio_chip;
  52         struct pinctrl_gpio_range gpio_range;
  53
  54 -       struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
  55 +       struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
  56         spinlock_t irq_lock[BCM2835_NUM_BANKS];
  57  };
  58
  59 @@ -385,17 +386,16 @@ static struct gpio_chip bcm2835_gpio_chi
  60         .can_sleep = false,
  61  };
  62
  63 -static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
  64 +static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
  65 +                                       unsigned int bank, u32 mask)
  66  {
  67 -       struct bcm2835_gpio_irqdata *irqdata = dev_id;
  68 -       struct bcm2835_pinctrl *pc = irqdata->pc;
  69 -       int bank = irqdata->bank;
  70         unsigned long events;
  71         unsigned offset;
  72         unsigned gpio;
  73         unsigned int type;
  74
  75         events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
  76 +       events &= mask;
  77         events &= pc->enabled_irq_map[bank];
  78         for_each_set_bit(offset, &events, 32) {
  79                 gpio = (32 * bank) + offset;
  80 @@ -403,7 +403,30 @@ static irqreturn_t bcm2835_gpio_irq_hand
  81
  82                 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
  83         }
  84 -       return events ? IRQ_HANDLED : IRQ_NONE;
  85 +
  86 +       return (events != 0);
  87 +}
  88 +
  89 +static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
  90 +{
  91 +       struct bcm2835_gpio_irqdata *irqdata = dev_id;
  92 +       struct bcm2835_pinctrl *pc = irqdata->pc;
  93 +       int handled = 0;
  94 +
  95 +       switch (irqdata->irqgroup) {
  96 +       case 0: /* IRQ0 covers GPIOs 0-27 */
  97 +               handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
  98 +               break;
  99 +       case 1: /* IRQ1 covers GPIOs 28-45 */
 100 +               handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
 101 +                         bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
 102 +               break;
 103 +       case 2: /* IRQ2 covers GPIOs 46-53 */
 104 +               handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
 105 +               break;
 106 +       }
 107 +
 108 +       return handled ? IRQ_HANDLED : IRQ_NONE;
 109  }
 110
 111  static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
 112 @@ -992,8 +1015,6 @@ static int bcm2835_pinctrl_probe(struct
 113         for (i = 0; i < BCM2835_NUM_BANKS; i++) {
 114                 unsigned long events;
 115                 unsigned offset;
 116 -               int len;
 117 -               char *name;
 118
 119                 /* clear event detection flags */
 120                 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
 121 @@ -1008,10 +1029,15 @@ static int bcm2835_pinctrl_probe(struct
 122                 for_each_set_bit(offset, &events, 32)
 123                         bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
 124
 125 +               spin_lock_init(&pc->irq_lock[i]);
 126 +       }
 127 +
 128 +       for (i = 0; i < BCM2835_NUM_IRQS; i++) {
 129 +               int len;
 130 +               char *name;
 131                 pc->irq[i] = irq_of_parse_and_map(np, i);
 132                 pc->irq_data[i].pc = pc;
 133 -               pc->irq_data[i].bank = i;
 134 -               spin_lock_init(&pc->irq_lock[i]);
 135 +               pc->irq_data[i].irqgroup = i;
 136
 137                 len = strlen(dev_name(pc->dev)) + 16;
 138                 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
 139 @@ -1068,6 +1094,7 @@ static struct platform_driver bcm2835_pi
 140         .remove = bcm2835_pinctrl_remove,
 141         .driver = {
 142                 .name = MODULE_NAME,
 143 +               .owner = THIS_MODULE,
 144                 .of_match_table = bcm2835_pinctrl_match,
 145         },
 146  };