git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From 25291f86f449c4488a0a46b1e6b3ce3b83dbf1f9 Mon Sep 17 00:00:00 2001
   2 From: Xiaowei Bao <xiaowei.bao@nxp.com>
   3 Date: Wed, 15 May 2019 10:14:30 +0800
   4 Subject: [PATCH] arm64: dts: ls1028a: Add PCIe controller DT nodes
   5
   6 LS1028a implements 2 PCIe 3.0 controllers.
   7
   8 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
   9 ---
  10  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 50 ++++++++++++++++++++++++++
  11  1 file changed, 50 insertions(+)
  12
  13 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  14 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  15 @@ -631,6 +631,56 @@
  16                         };
  17                 };
  18
  19 +               pcie@3400000 {
  20 +                       compatible = "fsl,ls1028a-pcie";
  21 +                       reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
  22 +                              0x80 0x00000000 0x0 0x00002000>; /* configuration space */
  23 +                       reg-names = "regs", "config";
  24 +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
  25 +                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
  26 +                       interrupt-names = "pme", "aer";
  27 +                       #address-cells = <3>;
  28 +                       #size-cells = <2>;
  29 +                       device_type = "pci";
  30 +                       dma-coherent;
  31 +                       bus-range = <0x0 0xff>;
  32 +                       ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
  33 +                                 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  34 +                       msi-parent = <&its>;
  35 +                       #interrupt-cells = <1>;
  36 +                       interrupt-map-mask = <0 0 0 7>;
  37 +                       interrupt-map = <0000 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  38 +                                       <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  39 +                                       <0000 0 0 3 &gic GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
  40 +                                       <0000 0 0 4 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  41 +                       status = "disabled";
  42 +               };
  43 +
  44 +               pcie@3500000 {
  45 +                       compatible = "fsl,ls1028a-pcie";
  46 +                       reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
  47 +                              0x88 0x00000000 0x0 0x00002000>; /* configuration space */
  48 +                       reg-names = "regs", "config";
  49 +                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  50 +                                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  51 +                       interrupt-names = "pme", "aer";
  52 +                       #address-cells = <3>;
  53 +                       #size-cells = <2>;
  54 +                       device_type = "pci";
  55 +                       dma-coherent;
  56 +                       bus-range = <0x0 0xff>;
  57 +                       ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */
  58 +                                 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  59 +                       msi-parent = <&its>;
  60 +                       #interrupt-cells = <1>;
  61 +                       interrupt-map-mask = <0 0 0 7>;
  62 +                       interrupt-map = <0000 0 0 1 &gic GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  63 +                                       <0000 0 0 2 &gic GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  64 +                                       <0000 0 0 3 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  65 +                                       <0000 0 0 4 &gic GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
  66 +                       status = "disabled";
  67 +               };
  68 +
  69                 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
  70                         compatible = "pci-host-ecam-generic";
  71                         reg = <0x01 0xf0000000 0x0 0x100000>;