projects / openwrt / staging / 981213.git / blob
? search:


7a0b285f2ca3a344a9b0a58837faa5f4ead08987
[openwrt/staging/981213.git] /
1 From db797ae0542220a98658229397da464c383c991c Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 25 Jul 2023 01:53:13 +0100
4 Subject: [PATCH 103/250] net: ethernet: mtk_eth_soc: convert caps in
5 mtk_soc_data struct to u64
6
7 This is a preliminary patch to introduce support for MT7988 SoC.
8
9 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
10 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
11 Link: https://lore.kernel.org/r/9499ac3670b2fc5b444404b84e8a4a169beabbf2.1690246066.git.daniel@makrotopia.org
12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
13 ---
14 drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 ++++----
15 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 56 ++++++++++----------
16 2 files changed, 39 insertions(+), 39 deletions(-)
17
18 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
19 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
20 @@ -15,10 +15,10 @@
21 struct mtk_eth_muxc {
22 const char *name;
23 int cap_bit;
24 - int (*set_path)(struct mtk_eth *eth, int path);
25 + int (*set_path)(struct mtk_eth *eth, u64 path);
26 };
27
28 -static const char *mtk_eth_path_name(int path)
29 +static const char *mtk_eth_path_name(u64 path)
30 {
31 switch (path) {
32 case MTK_ETH_PATH_GMAC1_RGMII:
33 @@ -40,7 +40,7 @@ static const char *mtk_eth_path_name(int
34 }
35 }
36
37 -static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path)
38 +static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
39 {
40 bool updated = true;
41 u32 val, mask, set;
42 @@ -71,7 +71,7 @@ static int set_mux_gdm1_to_gmac1_esw(str
43 return 0;
44 }
45
46 -static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path)
47 +static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path)
48 {
49 unsigned int val = 0;
50 bool updated = true;
51 @@ -94,7 +94,7 @@ static int set_mux_gmac2_gmac0_to_gephy(
52 return 0;
53 }
54
55 -static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
56 +static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
57 {
58 unsigned int val = 0, mask = 0, reg = 0;
59 bool updated = true;
60 @@ -125,7 +125,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
61 return 0;
62 }
63
64 -static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path)
65 +static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
66 {
67 unsigned int val = 0;
68 bool updated = true;
69 @@ -163,7 +163,7 @@ static int set_mux_gmac1_gmac2_to_sgmii_
70 return 0;
71 }
72
73 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path)
74 +static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
75 {
76 unsigned int val = 0;
77 bool updated = true;
78 @@ -218,7 +218,7 @@ static const struct mtk_eth_muxc mtk_eth
79 },
80 };
81
82 -static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)
83 +static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path)
84 {
85 int i, err = 0;
86
87 @@ -249,7 +249,7 @@ out:
88
89 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
90 {
91 - int path;
92 + u64 path;
93
94 path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
95 MTK_ETH_PATH_GMAC2_SGMII;
96 @@ -260,7 +260,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk
97
98 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
99 {
100 - int path = 0;
101 + u64 path = 0;
102
103 if (mac_id == 1)
104 path = MTK_ETH_PATH_GMAC2_GEPHY;
105 @@ -274,7 +274,7 @@ int mtk_gmac_gephy_path_setup(struct mtk
106
107 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
108 {
109 - int path;
110 + u64 path;
111
112 path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_RGMII :
113 MTK_ETH_PATH_GMAC2_RGMII;
114 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
115 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
116 @@ -866,41 +866,41 @@ enum mkt_eth_capabilities {
117 };
118
119 /* Supported hardware group on SoCs */
120 -#define MTK_RGMII BIT(MTK_RGMII_BIT)
121 -#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
122 -#define MTK_SGMII BIT(MTK_SGMII_BIT)
123 -#define MTK_ESW BIT(MTK_ESW_BIT)
124 -#define MTK_GEPHY BIT(MTK_GEPHY_BIT)
125 -#define MTK_MUX BIT(MTK_MUX_BIT)
126 -#define MTK_INFRA BIT(MTK_INFRA_BIT)
127 -#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
128 -#define MTK_HWLRO BIT(MTK_HWLRO_BIT)
129 -#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
130 -#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
131 -#define MTK_QDMA BIT(MTK_QDMA_BIT)
132 -#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
133 -#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
134 -#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
135 +#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
136 +#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
137 +#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
138 +#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
139 +#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
140 +#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
141 +#define MTK_INFRA BIT_ULL(MTK_INFRA_BIT)
142 +#define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT)
143 +#define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT)
144 +#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT)
145 +#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
146 +#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT)
147 +#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT)
148 +#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
149 +#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
150
151 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
152 - BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
153 + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
154 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
155 - BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
156 + BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
157 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
158 - BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
159 + BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
160 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
161 - BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
162 + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
163 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
164 - BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
165 + BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
166
167 /* Supported path present on SoCs */
168 -#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
169 -#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
170 -#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
171 -#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
172 -#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
173 -#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
174 -#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
175 +#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
176 +#define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
177 +#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
178 +#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
179 +#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
180 +#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
181 +#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
182
183 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
184 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
185 @@ -1045,7 +1045,7 @@ struct mtk_reg_map {
186 struct mtk_soc_data {
187 const struct mtk_reg_map *reg_map;
188 u32 ana_rgc3;
189 - u32 caps;
190 + u64 caps;
191 u32 required_clks;
192 bool required_pctl;
193 u8 offload_version;
Staging tree of Chuanhong Guo