7a8d1c06b2d3f7a5463120b1412586a6619aa217
[openwrt/staging/ynezz.git] /
1 From 269f19c848a2380db03a3f207cafb88e28d71c53 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Sun, 24 Mar 2013 19:26:28 +0100
4 Subject: [PATCH] rt2x00: rt2800lib: add channel configuration code for RT3883
5
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 ---
8 drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 72 +++++++++++++++++++++++++++++--
9 1 file changed, 69 insertions(+), 3 deletions(-)
10
11 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
12 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
13 @@ -3741,6 +3741,36 @@ static char rt2800_txpower_to_dev(struct
14 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
15 }
16
17 +static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
18 + struct rf_channel *rf)
19 +{
20 + u8 bbp;
21 +
22 + bbp = (rf->channel > 14) ? 0x48 : 0x38;
23 + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
24 +
25 + rt2800_bbp_write(rt2x00dev, 69, 0x12);
26 +
27 + if (rf->channel <= 14) {
28 + rt2800_bbp_write(rt2x00dev, 70, 0x0a);
29 + } else {
30 + /* Disable CCK packet detection */
31 + rt2800_bbp_write(rt2x00dev, 70, 0x00);
32 + }
33 +
34 + rt2800_bbp_write(rt2x00dev, 73, 0x10);
35 +
36 + if (rf->channel > 14) {
37 + rt2800_bbp_write(rt2x00dev, 62, 0x1d);
38 + rt2800_bbp_write(rt2x00dev, 63, 0x1d);
39 + rt2800_bbp_write(rt2x00dev, 64, 0x1d);
40 + } else {
41 + rt2800_bbp_write(rt2x00dev, 62, 0x2d);
42 + rt2800_bbp_write(rt2x00dev, 63, 0x2d);
43 + rt2800_bbp_write(rt2x00dev, 64, 0x2d);
44 + }
45 +}
46 +
47 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
48 struct ieee80211_conf *conf,
49 struct rf_channel *rf,
50 @@ -3759,6 +3789,12 @@ static void rt2800_config_channel(struct
51 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
52 info->default_power3);
53
54 + switch (rt2x00dev->chip.rt) {
55 + case RT3883:
56 + rt3883_bbp_adjust(rt2x00dev, rf);
57 + break;
58 + }
59 +
60 switch (rt2x00dev->chip.rf) {
61 case RF2020:
62 case RF3020:
63 @@ -3863,6 +3899,15 @@ static void rt2800_config_channel(struct
64 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
65 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
66 rt2800_bbp_write(rt2x00dev, 77, 0x98);
67 + } else if (rt2x00_rt(rt2x00dev, RT3883)) {
68 + rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
69 + rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
70 + rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
71 +
72 + if (rt2x00dev->default_ant.rx_chain_num > 1)
73 + rt2800_bbp_write(rt2x00dev, 86, 0x46);
74 + else
75 + rt2800_bbp_write(rt2x00dev, 86, 0);
76 } else {
77 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
78 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
79 @@ -3876,6 +3921,7 @@ static void rt2800_config_channel(struct
80 !rt2x00_rt(rt2x00dev, RT6352)) {
81 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
82 rt2800_bbp_write(rt2x00dev, 82, 0x62);
83 + rt2800_bbp_write(rt2x00dev, 82, 0x62);
84 rt2800_bbp_write(rt2x00dev, 75, 0x46);
85 } else {
86 if (rt2x00_rt(rt2x00dev, RT3593))
87 @@ -3884,19 +3930,22 @@ static void rt2800_config_channel(struct
88 rt2800_bbp_write(rt2x00dev, 82, 0x84);
89 rt2800_bbp_write(rt2x00dev, 75, 0x50);
90 }
91 - if (rt2x00_rt(rt2x00dev, RT3593))
92 + if (rt2x00_rt(rt2x00dev, RT3593) ||
93 + rt2x00_rt(rt2x00dev, RT3883))
94 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
95 }
96
97 } else {
98 if (rt2x00_rt(rt2x00dev, RT3572))
99 rt2800_bbp_write(rt2x00dev, 82, 0x94);
100 - else if (rt2x00_rt(rt2x00dev, RT3593))
101 + else if (rt2x00_rt(rt2x00dev, RT3593) ||
102 + rt2x00_rt(rt2x00dev, RT3883))
103 rt2800_bbp_write(rt2x00dev, 82, 0x82);
104 else if (!rt2x00_rt(rt2x00dev, RT6352))
105 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
106
107 - if (rt2x00_rt(rt2x00dev, RT3593))
108 + if (rt2x00_rt(rt2x00dev, RT3593) ||
109 + rt2x00_rt(rt2x00dev, RT3883))
110 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
111
112 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
113 @@ -4022,6 +4071,23 @@ static void rt2800_config_channel(struct
114
115 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
116
117 + usleep_range(1000, 1500);
118 + }
119 +
120 + if (rt2x00_rt(rt2x00dev, RT3883)) {
121 + if (!conf_is_ht40(conf))
122 + rt2800_bbp_write(rt2x00dev, 105, 0x34);
123 + else
124 + rt2800_bbp_write(rt2x00dev, 105, 0x04);
125 +
126 + /* AGC init */
127 + if (rf->channel <= 14)
128 + reg = 0x2e + rt2x00dev->lna_gain;
129 + else
130 + reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
131 +
132 + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
133 +
134 usleep_range(1000, 1500);
135 }
136