git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 5e06e9a78bbc81f64fdb4c8502a8e7175d8b6216 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 27 Jul 2022 10:03:17 +0800
   4 Subject: [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986
   5
   6 This patch adds support for MediaTek MT7981 and MT7986. Both chips uses
   7 PDMA v2.
   8
   9 Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  drivers/net/mtk_eth.c | 27 +++++++++++++++++++++++++++
  13  drivers/net/mtk_eth.h |  5 +++++
  14  2 files changed, 32 insertions(+)
  15
  16 --- a/drivers/net/mtk_eth.c
  17 +++ b/drivers/net/mtk_eth.c
  18 @@ -115,6 +115,7 @@ struct mtk_eth_priv {
  19         int force_mode;
  20         int speed;
  21         int duplex;
  22 +       bool pn_swap;
  23
  24         struct phy_device *phydev;
  25         int phy_interface;
  26 @@ -1057,6 +1058,12 @@ static void mtk_sgmii_init(struct mtk_et
  27         /* SGMII force mode setting */
  28         writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
  29
  30 +       /* SGMII PN SWAP setting */
  31 +       if (priv->pn_swap) {
  32 +               setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
  33 +                            SGMII_PN_SWAP_TX_RX);
  34 +       }
  35 +
  36         /* Release PHYA power down state */
  37         clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
  38                         SGMII_PHYA_PWD, 0);
  39 @@ -1470,6 +1477,8 @@ static int mtk_eth_of_to_plat(struct ude
  40                         dev_err(dev, "Unable to find sgmii\n");
  41                         return -ENODEV;
  42                 }
  43 +
  44 +               priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
  45         }
  46
  47         /* check for switch first, otherwise phy will be used */
  48 @@ -1520,6 +1529,22 @@ static int mtk_eth_of_to_plat(struct ude
  49         return 0;
  50  }
  51
  52 +static const struct mtk_soc_data mt7986_data = {
  53 +       .caps = MT7986_CAPS,
  54 +       .ana_rgc3 = 0x128,
  55 +       .pdma_base = PDMA_V2_BASE,
  56 +       .txd_size = sizeof(struct mtk_tx_dma_v2),
  57 +       .rxd_size = sizeof(struct mtk_rx_dma_v2),
  58 +};
  59 +
  60 +static const struct mtk_soc_data mt7981_data = {
  61 +       .caps = MT7986_CAPS,
  62 +       .ana_rgc3 = 0x128,
  63 +       .pdma_base = PDMA_V2_BASE,
  64 +       .txd_size = sizeof(struct mtk_tx_dma_v2),
  65 +       .rxd_size = sizeof(struct mtk_rx_dma_v2),
  66 +};
  67 +
  68  static const struct mtk_soc_data mt7629_data = {
  69         .ana_rgc3 = 0x128,
  70         .pdma_base = PDMA_V1_BASE,
  71 @@ -1549,6 +1574,8 @@ static const struct mtk_soc_data mt7621_
  72  };
  73
  74  static const struct udevice_id mtk_eth_ids[] = {
  75 +       { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
  76 +       { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
  77         { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
  78         { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
  79         { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
  80 --- a/drivers/net/mtk_eth.h
  81 +++ b/drivers/net/mtk_eth.h
  82 @@ -36,6 +36,8 @@ enum mkt_eth_capabilities {
  83
  84  #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
  85
  86 +#define MT7986_CAPS  (MTK_NETSYS_V2)
  87 +
  88  /* Frame Engine Register Bases */
  89  #define PDMA_V1_BASE                   0x0800
  90  #define PDMA_V2_BASE                   0x6000
  91 @@ -72,6 +74,9 @@ enum mkt_eth_capabilities {
  92  #define SGMSYS_QPHY_PWR_STATE_CTRL     0xe8
  93  #define SGMII_PHYA_PWD                 BIT(4)
  94
  95 +#define SGMSYS_QPHY_WRAP_CTRL          0xec
  96 +#define SGMII_PN_SWAP_TX_RX            0x03
  97 +
  98  #define SGMSYS_GEN2_SPEED              0x2028
  99  #define SGMSYS_GEN2_SPEED_V2           0x128
 100  #define SGMSYS_SPEED_2500              BIT(2)