git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 916df9ddac295df428a304fd03ed492ad10e900c Mon Sep 17 00:00:00 2001
   2 From: Marc Kleine-Budde <mkl@pengutronix.de>
   3 Date: Fri, 1 Mar 2019 10:22:26 +0100
   4 Subject: [PATCH] can: flexcan: remove TX mailbox bit from struct
   5  flexcan_priv::rx_mask{1,2}
   6
   7 The flexcan IP core has up to 64 mailboxes, each one has a corresponding
   8 interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
   9 imask1 or imask2 registers.
  10
  11 In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
  12 non RX interrupt sources and uses the precomputed values rx_mask1 and
  13 rx_mask2 of struct flexcan_priv for this.
  14
  15 Currently these values cannot be used directly, as they contain the TX
  16 mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1
  17 and flexcan_priv::rx_mask2, and sets the TX flag directly when writing
  18 the regs->iflag1 and regs->iflag2 into the hardware.
  19
  20 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
  21 ---
  22  drivers/net/can/flexcan.c | 14 +++++---------
  23  1 file changed, 5 insertions(+), 9 deletions(-)
  24
  25 --- a/drivers/net/can/flexcan.c
  26 +++ b/drivers/net/can/flexcan.c
  27 @@ -880,8 +880,7 @@ static inline u64 flexcan_read_reg_iflag
  28         struct flexcan_regs __iomem *regs = priv->regs;
  29         u32 iflag1, iflag2;
  30
  31 -       iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2 &
  32 -               ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
  33 +       iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2;
  34         iflag1 = priv->read(&regs->iflag1) & priv->rx_mask1;
  35
  36         return (u64)iflag2 << 32 | iflag1;
  37 @@ -1228,7 +1227,7 @@ static int flexcan_chip_start(struct net
  38         disable_irq(dev->irq);
  39         priv->write(priv->reg_ctrl_default, &regs->ctrl);
  40         priv->write(priv->rx_mask1, &regs->imask1);
  41 -       priv->write(priv->rx_mask2, &regs->imask2);
  42 +       priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), &regs->imask2);
  43         enable_irq(dev->irq);
  44
  45         /* print chip status */
  46 @@ -1322,9 +1321,6 @@ static int flexcan_open(struct net_devic
  47         priv->tx_mb_idx = priv->mb_count - 1;
  48         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
  49
  50 -       priv->rx_mask1 = 0;
  51 -       priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
  52 -
  53         priv->offload.mailbox_read = flexcan_mailbox_read;
  54
  55         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
  56 @@ -1335,12 +1331,12 @@ static int flexcan_open(struct net_devic
  57
  58                 imask = GENMASK_ULL(priv->offload.mb_last,
  59                                     priv->offload.mb_first);
  60 -               priv->rx_mask1 |= imask;
  61 -               priv->rx_mask2 |= imask >> 32;
  62 +               priv->rx_mask1 = imask;
  63 +               priv->rx_mask2 = imask >> 32;
  64
  65                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
  66         } else {
  67 -               priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
  68 +               priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
  69                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
  70                 err = can_rx_offload_add_fifo(dev, &priv->offload,
  71                                               FLEXCAN_NAPI_WEIGHT);