git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From b565d66403e3df303a058c0d8d00d0fc6aeb2ddc Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sat, 26 Feb 2022 14:52:31 +0100
   4 Subject: [PATCH 11/14] dt-bindings: clock: add ipq8064 ce5 clk define
   5
   6 Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
   7 Define CE5_SRC is not used so it's OK to change and we align it to
   8 the QSDK naming.
   9
  10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  11 Acked-by: Rob Herring <robh@kernel.org>
  12 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
  13 Tested-by: Jonathan McDowell <noodles@earth.li>
  14 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  15 Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com
  16 ---
  17  include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
  18  1 file changed, 4 insertions(+), 1 deletion(-)
  19
  20 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
  21 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
  22 @@ -240,7 +240,7 @@
  23  #define PLL14                                  232
  24  #define PLL14_VOTE                             233
  25  #define PLL18                                  234
  26 -#define CE5_SRC                                        235
  27 +#define CE5_A_CLK                              235
  28  #define CE5_H_CLK                              236
  29  #define CE5_CORE_CLK                           237
  30  #define CE3_SLEEP_CLK                          238
  31 @@ -283,5 +283,8 @@
  32  #define EBI2_AON_CLK                           281
  33  #define NSSTCM_CLK_SRC                         282
  34  #define NSSTCM_CLK                             283
  35 +#define CE5_A_CLK_SRC                          285
  36 +#define CE5_H_CLK_SRC                          286
  37 +#define CE5_CORE_CLK_SRC                       287
  38
  39  #endif