git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From 5d35ff6d904bcbf00bee99ea493db47360e756bc Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Thu, 21 Dec 2017 13:32:09 -0800
   4 Subject: [PATCH 184/454] drm/vc4: Flush the caches before the render jobs, as
   5  well.
   6
   7 If the frame samples from a render target that was just written, its
   8 cache flush during the binning step may have occurred before the
   9 previous frame's RCL was completed.  Flush the texture caches again
  10 before starting each RCL job to make sure that the sampling of the
  11 previous RCL's output is correct.
  12
  13 Fixes flickering in the top left of 3DMMES Taiji.
  14
  15 Signed-off-by: Eric Anholt <eric@anholt.net>
  16 Fixes: ca26d28bbaa3 ("drm/vc4: improve throughput by pipelining binning and rendering jobs")
  17 ---
  18  drivers/gpu/drm/vc4/vc4_gem.c | 21 +++++++++++++++++++++
  19  1 file changed, 21 insertions(+)
  20
  21 --- a/drivers/gpu/drm/vc4/vc4_gem.c
  22 +++ b/drivers/gpu/drm/vc4/vc4_gem.c
  23 @@ -436,6 +436,19 @@ vc4_flush_caches(struct drm_device *dev)
  24                   VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
  25  }
  26
  27 +static void
  28 +vc4_flush_texture_caches(struct drm_device *dev)
  29 +{
  30 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
  31 +
  32 +       V3D_WRITE(V3D_L2CACTL,
  33 +                 V3D_L2CACTL_L2CCLR);
  34 +
  35 +       V3D_WRITE(V3D_SLCACTL,
  36 +                 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
  37 +                 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC));
  38 +}
  39 +
  40  /* Sets the registers for the next job to be actually be executed in
  41   * the hardware.
  42   *
  43 @@ -474,6 +487,14 @@ vc4_submit_next_render_job(struct drm_de
  44         if (!exec)
  45                 return;
  46
  47 +       /* A previous RCL may have written to one of our textures, and
  48 +        * our full cache flush at bin time may have occurred before
  49 +        * that RCL completed.  Flush the texture cache now, but not
  50 +        * the instructions or uniforms (since we don't write those
  51 +        * from an RCL).
  52 +        */
  53 +       vc4_flush_texture_caches(dev);
  54 +
  55         submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
  56  }
  57