git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From d0f6e84d284870eda4a544002eb5ed0dce3d8680 Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Mon, 8 Jan 2024 17:10:44 +0000
   4 Subject: [PATCH 0835/1085] mmc: sdhci-brcmstb: remove 32-bit accessors for
   5  BCM2712
   6
   7 The reason for adding these are lost to the mists of time (and for a
   8 previous chip revision). Removing these accessors appears to have no ill
   9 effect on production chips, so get rid of the unnecessary RMW cycles.
  10
  11 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  12 ---
  13  drivers/mmc/host/Kconfig         |   1 -
  14  drivers/mmc/host/sdhci-brcmstb.c | 117 -------------------------------
  15  2 files changed, 118 deletions(-)
  16
  17 --- a/drivers/mmc/host/Kconfig
  18 +++ b/drivers/mmc/host/Kconfig
  19 @@ -1039,7 +1039,6 @@ config MMC_SDHCI_BRCMSTB
  20         tristate "Broadcom SDIO/SD/MMC support"
  21         depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
  22         depends on MMC_SDHCI_PLTFM
  23 -       select MMC_SDHCI_IO_ACCESSORS
  24         select MMC_CQHCI
  25         select OF_DYNAMIC
  26         default ARCH_BRCMSTB || BMIPS_GENERIC
  27 --- a/drivers/mmc/host/sdhci-brcmstb.c
  28 +++ b/drivers/mmc/host/sdhci-brcmstb.c
  29 @@ -49,10 +49,6 @@ struct sdhci_brcmstb_priv {
  30         unsigned int flags;
  31         struct clk *base_clk;
  32         u32 base_freq_hz;
  33 -       u32 shadow_cmd;
  34 -       u32 shadow_blk;
  35 -       bool is_cmd_shadowed;
  36 -       bool is_blk_shadowed;
  37         struct regulator *sde_1v8;
  38         struct device_node *sde_pcie;
  39         void *__iomem sde_ioaddr;
  40 @@ -121,113 +117,6 @@ static void sdhci_brcmstb_set_clock(stru
  41         sdhci_enable_clk(host, clk);
  42  }
  43
  44 -#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
  45 -
  46 -static inline u32 sdhci_brcmstb_32only_readl(struct sdhci_host *host, int reg)
  47 -{
  48 -       u32 val = readl(host->ioaddr + reg);
  49 -
  50 -       pr_debug("%s: readl [0x%02x] 0x%08x\n",
  51 -                mmc_hostname(host->mmc), reg, val);
  52 -       return val;
  53 -}
  54 -
  55 -static u16 sdhci_brcmstb_32only_readw(struct sdhci_host *host, int reg)
  56 -{
  57 -       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  58 -       struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
  59 -       u32 val;
  60 -       u16 word;
  61 -
  62 -       if ((reg == SDHCI_TRANSFER_MODE) && brcmstb_priv->is_cmd_shadowed) {
  63 -               /* Get the saved transfer mode */
  64 -               val = brcmstb_priv->shadow_cmd;
  65 -       } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
  66 -                  brcmstb_priv->is_blk_shadowed) {
  67 -               /* Get the saved block info */
  68 -               val = brcmstb_priv->shadow_blk;
  69 -       } else {
  70 -               val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
  71 -       }
  72 -       word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
  73 -       return word;
  74 -}
  75 -
  76 -static u8 sdhci_brcmstb_32only_readb(struct sdhci_host *host, int reg)
  77 -{
  78 -       u32 val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
  79 -       u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
  80 -       return byte;
  81 -}
  82 -
  83 -static inline void sdhci_brcmstb_32only_writel(struct sdhci_host *host, u32 val, int reg)
  84 -{
  85 -       pr_debug("%s: writel [0x%02x] 0x%08x\n",
  86 -                mmc_hostname(host->mmc), reg, val);
  87 -
  88 -       writel(val, host->ioaddr + reg);
  89 -}
  90 -
  91 -/*
  92 - * BCM2712 unfortunately carries with it a perennial bug with the SD controller
  93 - * register interface present on previous chips (2711/2709/2708). Accesses must
  94 - * be dword-sized and a read-modify-write cycle to the 32-bit registers
  95 - * containing the COMMAND, TRANSFER_MODE, BLOCK_SIZE and BLOCK_COUNT registers
  96 - * tramples the upper/lower 16 bits of data written. BCM2712 does not seem to
  97 - * need the extreme delay between each write as on previous chips, just the
  98 - * serialisation of writes to these registers in a single 32-bit operation.
  99 - */
 100 -static void sdhci_brcmstb_32only_writew(struct sdhci_host *host, u16 val, int reg)
 101 -{
 102 -       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 103 -       struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
 104 -       u32 word_shift = REG_OFFSET_IN_BITS(reg);
 105 -       u32 mask = 0xffff << word_shift;
 106 -       u32 oldval, newval;
 107 -
 108 -       if (reg == SDHCI_COMMAND) {
 109 -               /* Write the block now as we are issuing a command */
 110 -               if (brcmstb_priv->is_blk_shadowed) {
 111 -                       sdhci_brcmstb_32only_writel(host, brcmstb_priv->shadow_blk,
 112 -                               SDHCI_BLOCK_SIZE);
 113 -                       brcmstb_priv->is_blk_shadowed = false;
 114 -               }
 115 -               oldval = brcmstb_priv->shadow_cmd;
 116 -               brcmstb_priv->is_cmd_shadowed = false;
 117 -       } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
 118 -                  brcmstb_priv->is_blk_shadowed) {
 119 -               /* Block size and count are stored in shadow reg */
 120 -               oldval = brcmstb_priv->shadow_blk;
 121 -       } else {
 122 -               /* Read reg, all other registers are not shadowed */
 123 -               oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
 124 -       }
 125 -       newval = (oldval & ~mask) | (val << word_shift);
 126 -
 127 -       if (reg == SDHCI_TRANSFER_MODE) {
 128 -               /* Save the transfer mode until the command is issued */
 129 -               brcmstb_priv->shadow_cmd = newval;
 130 -               brcmstb_priv->is_cmd_shadowed = true;
 131 -       } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
 132 -               /* Save the block info until the command is issued */
 133 -               brcmstb_priv->shadow_blk = newval;
 134 -               brcmstb_priv->is_blk_shadowed = true;
 135 -       } else {
 136 -               /* Command or other regular 32-bit write */
 137 -               sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
 138 -       }
 139 -}
 140 -
 141 -static void sdhci_brcmstb_32only_writeb(struct sdhci_host *host, u8 val, int reg)
 142 -{
 143 -       u32 oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
 144 -       u32 byte_shift = REG_OFFSET_IN_BITS(reg);
 145 -       u32 mask = 0xff << byte_shift;
 146 -       u32 newval = (oldval & ~mask) | (val << byte_shift);
 147 -
 148 -       sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
 149 -}
 150 -
 151  static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode,
 152                                   unsigned short vdd)
 153  {
 154 @@ -441,12 +330,6 @@ static struct sdhci_ops sdhci_brcmstb_op
 155  };
 156
 157  static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
 158 -       .read_l = sdhci_brcmstb_32only_readl,
 159 -       .read_w = sdhci_brcmstb_32only_readw,
 160 -       .read_b = sdhci_brcmstb_32only_readb,
 161 -       .write_l = sdhci_brcmstb_32only_writel,
 162 -       .write_w = sdhci_brcmstb_32only_writew,
 163 -       .write_b = sdhci_brcmstb_32only_writeb,
 164         .set_clock = sdhci_set_clock,
 165         .set_power = sdhci_brcmstb_set_power,
 166         .set_bus_width = sdhci_set_bus_width,