8abd264e794fbf408c1e0c92b8cdbca7f2dfe016
[openwrt/staging/stintel.git] /
1 From 13ad5ccc093ff448b99ac7e138e91e78796adb48 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Thu, 14 Oct 2021 00:39:12 +0200
4 Subject: dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll
5
6 Document qca,sgmii-enable-pll binding used in the CPU nodes to
7 enable SGMII PLL on MAC config.
8
9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
10 Signed-off-by: David S. Miller <davem@davemloft.net>
11 ---
12 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++
13 1 file changed, 10 insertions(+)
14
15 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
16 +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
17 @@ -45,6 +45,16 @@ A CPU port node has the following option
18 Mostly used in qca8327 with CPU port 0 set to
19 sgmii.
20 - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
21 +- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX
22 + chain along with Signal Detection.
23 + This should NOT be enabled for qca8327. If enabled with
24 + qca8327 the sgmii port won't correctly init and an err
25 + is printed.
26 + This can be required for qca8337 switch with revision 2.
27 + A warning is displayed when used with revision greater
28 + 2.
29 + With CPU port set to sgmii and qca8337 it is advised
30 + to set this unless a communication problem is observed.
31
32 For QCA8K the 'fixed-link' sub-node supports only the following properties:
33