git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 861a32edce13ccba86647507fefcfd4910972dd7 Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Thu, 14 Nov 2019 17:03:22 +0200
   4 Subject: [PATCH] net: mscc: ocelot: move invariant configs out of adjust_link
   5
   6 It doesn't make sense to rewrite all these registers every time the PHY
   7 library notifies us about a link state change.
   8
   9 In a future patch we will customize the MTU for the CPU port, and since
  10 the MTU was previously configured from adjust_link, if we don't make
  11 this change, its value would have got overridden.
  12
  13 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  15 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  16 Signed-off-by: David S. Miller <davem@davemloft.net>
  17 ---
  18  drivers/net/ethernet/mscc/ocelot.c | 85 +++++++++++++++++++-------------------
  19  1 file changed, 43 insertions(+), 42 deletions(-)
  20
  21 --- a/drivers/net/ethernet/mscc/ocelot.c
  22 +++ b/drivers/net/ethernet/mscc/ocelot.c
  23 @@ -408,7 +408,7 @@ static void ocelot_adjust_link(struct oc
  24                                struct phy_device *phydev)
  25  {
  26         struct ocelot_port *ocelot_port = ocelot->ports[port];
  27 -       int speed, atop_wm, mode = 0;
  28 +       int speed, mode = 0;
  29
  30         switch (phydev->speed) {
  31         case SPEED_10:
  32 @@ -440,32 +440,9 @@ static void ocelot_adjust_link(struct oc
  33         ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
  34                            mode, DEV_MAC_MODE_CFG);
  35
  36 -       /* Set MAC IFG Gaps
  37 -        * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
  38 -        * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
  39 -        */
  40 -       ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
  41 -                          DEV_MAC_IFG_CFG);
  42 -
  43 -       /* Load seed (0) and set MAC HDX late collision  */
  44 -       ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
  45 -                          DEV_MAC_HDX_CFG_SEED_LOAD,
  46 -                          DEV_MAC_HDX_CFG);
  47 -       mdelay(1);
  48 -       ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
  49 -                          DEV_MAC_HDX_CFG);
  50 -
  51         if (ocelot->ops->pcs_init)
  52                 ocelot->ops->pcs_init(ocelot, port);
  53
  54 -       /* Set Max Length and maximum tags allowed */
  55 -       ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
  56 -                          DEV_MAC_MAXLEN_CFG);
  57 -       ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
  58 -                          DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
  59 -                          DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
  60 -                          DEV_MAC_TAGS_CFG);
  61 -
  62         /* Enable MAC module */
  63         ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
  64                            DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
  65 @@ -475,22 +452,10 @@ static void ocelot_adjust_link(struct oc
  66         ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
  67                            DEV_CLOCK_CFG);
  68
  69 -       /* Set SMAC of Pause frame (00:00:00:00:00:00) */
  70 -       ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
  71 -       ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
  72 -
  73         /* No PFC */
  74         ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
  75                          ANA_PFC_PFC_CFG, port);
  76
  77 -       /* Set Pause WM hysteresis
  78 -        * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
  79 -        * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
  80 -        */
  81 -       ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
  82 -                        SYS_PAUSE_CFG_PAUSE_STOP(101) |
  83 -                        SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
  84 -
  85         /* Core: Enable port for frame transfer */
  86         ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
  87                          QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
  88 @@ -505,12 +470,6 @@ static void ocelot_adjust_link(struct oc
  89                          SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
  90                          SYS_MAC_FC_CFG, port);
  91         ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
  92 -
  93 -       /* Tail dropping watermark */
  94 -       atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
  95 -       ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
  96 -                        SYS_ATOP, port);
  97 -       ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
  98  }
  99
 100  static void ocelot_port_adjust_link(struct net_device *dev)
 101 @@ -2143,11 +2102,53 @@ static int ocelot_init_timestamp(struct
 102  static void ocelot_init_port(struct ocelot *ocelot, int port)
 103  {
 104         struct ocelot_port *ocelot_port = ocelot->ports[port];
 105 +       int atop_wm;
 106
 107         INIT_LIST_HEAD(&ocelot_port->skbs);
 108
 109         /* Basic L2 initialization */
 110
 111 +       /* Set MAC IFG Gaps
 112 +        * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
 113 +        * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
 114 +        */
 115 +       ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
 116 +                          DEV_MAC_IFG_CFG);
 117 +
 118 +       /* Load seed (0) and set MAC HDX late collision  */
 119 +       ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
 120 +                          DEV_MAC_HDX_CFG_SEED_LOAD,
 121 +                          DEV_MAC_HDX_CFG);
 122 +       mdelay(1);
 123 +       ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
 124 +                          DEV_MAC_HDX_CFG);
 125 +
 126 +       /* Set Max Length and maximum tags allowed */
 127 +       ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
 128 +                          DEV_MAC_MAXLEN_CFG);
 129 +       ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
 130 +                          DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
 131 +                          DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
 132 +                          DEV_MAC_TAGS_CFG);
 133 +
 134 +       /* Set SMAC of Pause frame (00:00:00:00:00:00) */
 135 +       ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
 136 +       ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
 137 +
 138 +       /* Set Pause WM hysteresis
 139 +        * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
 140 +        * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
 141 +        */
 142 +       ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
 143 +                        SYS_PAUSE_CFG_PAUSE_STOP(101) |
 144 +                        SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
 145 +
 146 +       /* Tail dropping watermark */
 147 +       atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
 148 +       ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
 149 +                        SYS_ATOP, port);
 150 +       ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
 151 +
 152         /* Drop frames with multicast source address */
 153         ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
 154                        ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,